csl_cachehal.h

SEED的VPM642测试程序-板级支持库

/******************************************************************************\
*           Copyright (C) 1999-2000 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_cachehal.h
* DATE CREATED.. 06/12/1999 
* LAST MODIFIED. 04/13/2001
*------------------------------------------------------------------------------
* REGISTERS
*
* CCFG     - cache configuration register
* L2FBAR   - L2 flush base address register
* L2FWC    - L2 flush word count register
* L2CBAR   - L2 clean base register
* L2CWC    - L2 clean word count register
* L1PFBAR  - L1P flush base address register
* L1PFWC   - L1P flush word count register
* L1DFBAR  - L1D flush base address register
* L1DFWC   - L1D flush word count register
* L2FLUSH  - L2 flush register
* L2CLEAN  - L2 clean register
*
*
*
*
*
* New Register Names based on SPRU609 for C621x/C671x
* and
* New Register Names based on SPRU610 for C64x
*
*
* L2WBAR   - L2 writeback base address register
* L2WWC    - L2 writeback word count register
* L2WIBAR  - L2 writeback-invalidate base address register
* L2WIWC   - L2 writeback-invalidate word count register
* L2IBAR   - L2 invalidate base address register(2)
* L2IWC    - L2 invalidate word count register(2)
* L1PIBAR  - L1P invalidate base address register
* L1PIWC   - L1P invalidate word count register
* L1DWIBAR - L1D writeback-invalidate base address register
* L1DWIWC  - L1D writeback-invalidate word count register
* L1DIBAR  - L1D invalidate base address register(2)
* L1DIWC   - L1D invalidate word count register(2)
* L2WB     - L2 writeback all register
* L2WBINV  - L2 writeback-invalidate all register
*
* MAR0     - memory attribute register 0
* MAR1     - memory attribute register 1
* ...      - ...
* MARn     - memory attribute register n (1)
* L2ALLOC0 - L2 Allocation register 0    (2)
* L2ALLOC1 - L2 Allocation register 1    (2)
* L2ALLOC2 - L2 Allocation register 2    (2)
* L2ALLOC3 - L2 Allocation register 3    (2)
*
* (1) n is different between C6x1x and C64x
* (2) C64x devices only
*
\******************************************************************************/
#ifndef _CSL_CACHEHAL_H_
#define _CSL_CACHEHAL_H_

#include <csl_stdinc.h>
#include <csl_chip.h>

#if (CACHE_SUPPORT)
/******************************************************************************\
* MISC section
\******************************************************************************/
#define _CACHE_BASE_GLOBAL  0x01840000u
#define CACHE_L2_SUPPORT L2CACHE_SUPPORT 


/******************************************************************************\
* module level register/field access macros
\******************************************************************************/

  /* ----------------- */
  /* FIELD MAKE MACROS */
  /* ----------------- */

  #define CACHE_FMK(REG,FIELD,x)\
    _PER_FMK(CACHE,##REG,##FIELD,x)

  #define CACHE_FMKS(REG,FIELD,SYM)\
    _PER_FMKS(CACHE,##REG,##FIELD,##SYM)
 
 
  /* -------------------------------- */
  /* RAW REGISTER/FIELD ACCESS MACROS */
  /* -------------------------------- */

  #define CACHE_ADDR(REG)\
    _CACHE_##REG##_ADDR

  #define CACHE_RGET(REG)\
    _PER_RGET(_CACHE_##REG##_ADDR,CACHE,##REG)

  #define CACHE_RSET(REG,x)\
    _PER_RSET(_CACHE_##REG##_ADDR,CACHE,##REG,x)

  #define CACHE_FGET(REG,FIELD)\
    _CACHE_##REG##_FGET(##FIELD)

  #define CACHE_FSET(REG,FIELD,x)\
    _CACHE_##REG##_FSET(##FIELD,x)

  #define CACHE_FSETS(REG,FIELD,SYM)\
    _CACHE_##REG##_FSETS(##FIELD,##SYM)
 
 
  /* ------------------------------------------ */
  /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */
  /* ------------------------------------------ */

  #define CACHE_RGETA(addr,REG)\
    _PER_RGET(addr,CACHE,##REG)

  #define CACHE_RSETA(addr,REG,x)\
    _PER_RSET(addr,CACHE,##REG,x)

  #define CACHE_FGETA(addr,REG,FIELD)\
    _PER_FGET(addr,CACHE,##REG,##FIELD)

  #define CACHE_FSETA(addr,REG,FIELD,x)\
    _PER_FSET(addr,CACHE,##REG,##FIELD,x)

  #define CACHE_FSETSA(addr,REG,FIELD,SYM)\
    _PER_FSETS(addr,CACHE,##REG,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  C C F G          |
* |___________________|
*
* CCFG - cache configuration register
*
* FIELDS (msb -> lsb)
* (rw) P (1)
* (w)  IP
* (w)  ID
* (rw) L2MODE
*
* (1) only supported for C64x devices
*
\******************************************************************************/
#if (L2CACHE_SUPPORT)
  #define _CACHE_CCFG_ADDR             0x01840000u

#if (C64_SUPPORT)
  #define _CACHE_CCFG_P_MASK           0xE0000000u
  #define _CACHE_CCFG_P_SHIFT          0x0000001Du
  #define  CACHE_CCFG_P_DEFAULT        0x00000000u
  #define  CACHE_CCFG_P_OF(x)          _VALUEOF(x)
  #define  CACHE_CCFG_P_URGENT         0x00000000u
  #define  CACHE_CCFG_P_HIGH           0x00000001u
  #define  CACHE_CCFG_P_MEDIUM         0x00000002u
  #define  CACHE_CCFG_P_LOW            0x00000003u
#endif

  #define _CACHE_CCFG_IP_MASK          0x00000200u
  #define _CACHE_CCFG_IP_SHIFT         0x00000009u
  #define  CACHE_CCFG_IP_DEFAULT       0x00000000u
  #define  CACHE_CCFG_IP_OF(x)         _VALUEOF(x)
  #define  CACHE_CCFG_IP_NORMAL        0x00000000u
  #define  CACHE_CCFG_IP_INVALIDATE    0x00000001u

  #define _CACHE_CCFG_ID_MASK          0x00000100u
  #define _CACHE_CCFG_ID_SHIFT         0x00000008u
  #define  CACHE_CCFG_ID_DEFAULT       0x00000000u
  #define  CACHE_CCFG_ID_OF(x)         _VALUEOF(x)
  #define  CACHE_CCFG_ID_NORMAL        0x00000000u
  #define  CACHE_CCFG_ID_INVALIDATE    0x00000001u

#if (!C64_SUPPORT)
  #define _CACHE_CCFG_L2MODE_MASK      0x00000007u
  #define _CACHE_CCFG_L2MODE_SHIFT     0x00000000u
  #define  CACHE_CCFG_L2MODE_DEFAULT   0x00000000u
  #define  CACHE_CCFG_L2MODE_OF(x)     _VALUEOF(x)
  #define  CACHE_CCFG_L2MODE_0KC       0x00000000u
  #define  CACHE_CCFG_L2MODE_16KC      0x00000001u
  #define  CACHE_CCFG_L2MODE_32KC      0x00000002u
  #define  CACHE_CCFG_L2MODE_48KC      0x00000003u
  #define  CACHE_CCFG_L2MODE_64KC      0x00000007u
#else 
  #define _CACHE_CCFG_L2MODE_MASK      0x00000007u
  #define _CACHE_CCFG_L2MODE_SHIFT     0x00000000u
  #define  CACHE_CCFG_L2MODE_DEFAULT   0x00000000u
  #define  CACHE_CCFG_L2MODE_OF(x)     _VALUEOF(x)
  #define  CACHE_CCFG_L2MODE_0KC       0x00000000u
  #define  CACHE_CCFG_L2MODE_32KC      0x00000001u
  #define  CACHE_CCFG_L2MODE_64KC      0x00000002u
  #define  CACHE_CCFG_L2MODE_128KC     0x00000003u
  #define  CACHE_CCFG_L2MODE_256KC     0x00000007u
#endif

  #define  CACHE_CCFG_OF(x)            _VALUEOF(x)

#if (!C64_SUPPORT)
  #define CACHE_CCFG_DEFAULT (Uint32)( \
     _PER_FDEFAULT(CACHE,CCFG,IP) \
    |_PER_FDEFAULT(CACHE,CCFG,ID) \
    |_PER_FDEFAULT(CACHE,CCFG,L2MODE) \
  )

  #define CACHE_CCFG_RMK(ip,id,l2mode) (Uint32)( \
     _PER_FMK(CACHE,CCFG,IP,ip) \
    |_PER_FMK(CACHE,CCFG,ID,id) \
    |_PER_FMK(CACHE,CCFG,L2MODE,l2mode) \
  )
#else 
  #define CACHE_CCFG_DEFAULT (Uint32)( \
     _PER_FDEFAULT(CACHE,CCFG,P) \
    |_PER_FDEFAULT(CACHE,CCFG,IP) \
    |_PER_FDEFAULT(CACHE,CCFG,ID) \
    |_PER_FDEFAULT(CACHE,CCFG,L2MODE) \
  )

  #define CACHE_CCFG_RMK(p,ip,id,l2mode) (Uint32)( \
     _PER_FMK(CACHE,CCFG,P,p) \
    |_PER_FMK(CACHE,CCFG,IP,ip) \
    |_PER_FMK(CACHE,CCFG,ID,id) \
    |_PER_FMK(CACHE,CCFG,L2MODE,l2mode) \
  )
#endif

  #define _CACHE_CCFG_FGET(FIELD)\
    _PER_FGET(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD)

  #define _CACHE_CCFG_FSET(FIELD,field)\
    _PER_FSET(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD,field)

  #define _CACHE_CCFG_FSETS(FIELD,SYM)\
    _PER_FSETS(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD,##SYM)

#endif /* L2CACHE_SUPPORT */


/******************************************************************************\
* _____________________
* |                   |
* |  L 2 F B A R      |
* |___________________|
*
* L2FBAR - L2 flush base address register
*
* Fields:
* (rw) L2FBAR
*
\******************************************************************************/
#if (L2CACHE_SUPPORT)
  #define _CACHE_L2FBAR_ADDR           0x01844000u

  #define _CACHE_L2FBAR_L2FBAR_MASK    0xFFFFFFFFu
  #define _CACHE_L2FBAR_L2FBAR_SHIFT   0x00000000u
  #define  CACHE_L2FBAR_L2FBAR_DEFAULT 0x00000000u
  #define  CACHE_L2FBAR_L2FBAR_OF(x)   _VALUEOF(x)

  #define  CACHE_L2FBAR_OF(x)          _VALUEOF(x)

  #define CACHE_L2FBAR_DEFAULT (Uint32)( \
     _PER_FDEFAULT(CACHE,L2FBAR,L2FBAR) \
  )

  #define CACHE_L2FBAR_RMK(l2fbar) (Uint32)( \
     _PER_FMK(CACHE,L2FBAR,L2FBAR,l2fbar) \
  )

  #define _CACHE_L2FBAR_FGET(FIELD)\
    _PER_FGET(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD)

  #define _CACHE_L2FBAR_FSET(FIELD,field)\
    _PER_FSET(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD,field)

  #define _CACHE_L2FBAR_FSETS(FIELD,SYM)\
    _PER_FSETS(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD,##SYM)
#endif


/******************************************************************************\
* _____________________
* |                   |
* |  L 2 F W C        |
* |___________________|
*
* L2FWC - L2 flush word count register
*
* Fields:
* (rw) L2FWC
*
\******************************************************************************/
#if (L2CACHE_SUPPORT)
  #define _CACHE_L2FWC_ADDR           0x01844004u

  #define _CACHE_L2FWC_L2FWC_MASK     0x0000FFFFu
  #define _CACHE_L2FWC_L2FWC_SHIFT    0x00000000u
  #define  CACHE_L2FWC_L2FWC_DEFAULT  0x00000000u
  #define  CACHE_L2FWC_L2FWC_OF(x)    _VALUEOF(x)

  #define  CACHE_L2FWC_OF(x)          _VALUEOF(x)

  #define CACHE_L2FWC_DEFAULT (Uint32)( \
     _PER_FDEFAULT(CACHE,L2FWC,L2FWC) \
  )

  #define CACHE_L2FWC_RMK(l2fwc) (Uint32)( \
     _PER_FMK(CACHE,L2FWC,L2FWC,l2fwc) \
  )

  #define _CACHE_L2FWC_FGET(FIELD)\
    _PER_FGET(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD)

  #define _CACHE_L2FWC_FSET(FIELD,field)\
    _PER_FSET(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD,field)

  #define _CACHE_L2FWC_FSETS(FIELD,SYM)\
    _PER_FSETS(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD,##SYM)