📄 csl_mcbsphal.h
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#define _MCBSP_RCR_RFRLEN1_SHIFT 0x00000008u
#define MCBSP_RCR_RFRLEN1_DEFAULT 0x00000000u
#define MCBSP_RCR_RFRLEN1_OF(x) _VALUEOF(x)
#define _MCBSP_RCR_RWDLEN1_MASK 0x000000E0u
#define _MCBSP_RCR_RWDLEN1_SHIFT 0x00000005u
#define MCBSP_RCR_RWDLEN1_DEFAULT 0x00000000u
#define MCBSP_RCR_RWDLEN1_OF(x) _VALUEOF(x)
#define MCBSP_RCR_RWDLEN1_8BIT 0x00000000u
#define MCBSP_RCR_RWDLEN1_12BIT 0x00000001u
#define MCBSP_RCR_RWDLEN1_16BIT 0x00000002u
#define MCBSP_RCR_RWDLEN1_20BIT 0x00000003u
#define MCBSP_RCR_RWDLEN1_24BIT 0x00000004u
#define MCBSP_RCR_RWDLEN1_32BIT 0x00000005u
#if (C11_SUPPORT || C64_SUPPORT)
#define _MCBSP_RCR_RWDREVRS_MASK 0x00000010u
#define _MCBSP_RCR_RWDREVRS_SHIFT 0x00000004u
#define MCBSP_RCR_RWDREVRS_DEFAULT 0x00000000u
#define MCBSP_RCR_RWDREVRS_OF(x) _VALUEOF(x)
#define MCBSP_RCR_RWDREVRS_DISABLE 0x00000000u
#define MCBSP_RCR_RWDREVRS_ENABLE 0x00000001u
#endif
#define MCBSP_RCR_OF(x) _VALUEOF(x)
#if (C11_SUPPORT || C64_SUPPORT)
#define MCBSP_RCR_DEFAULT (Uint32)(\
_PER_FDEFAULT(MCBSP,RCR,RPHASE)\
|_PER_FDEFAULT(MCBSP,RCR,RFRLEN2)\
|_PER_FDEFAULT(MCBSP,RCR,RWDLEN2)\
|_PER_FDEFAULT(MCBSP,RCR,RCOMPAND)\
|_PER_FDEFAULT(MCBSP,RCR,RFIG)\
|_PER_FDEFAULT(MCBSP,RCR,RDATDLY)\
|_PER_FDEFAULT(MCBSP,RCR,RFRLEN1)\
|_PER_FDEFAULT(MCBSP,RCR,RWDLEN1)\
|_PER_FDEFAULT(MCBSP,RCR,RWDREVRS)\
)
#define MCBSP_RCR_RMK(rphase,rfrlen2,rwdlen2,rcompand,rfig,\
rdatdly,rfrlen1,rwdlen1,rwdrevrs) (Uint32)(\
_PER_FMK(MCBSP,RCR,RPHASE,rphase)\
|_PER_FMK(MCBSP,RCR,RFRLEN2,rfrlen2)\
|_PER_FMK(MCBSP,RCR,RWDLEN2,rwdlen2)\
|_PER_FMK(MCBSP,RCR,RCOMPAND,rcompand)\
|_PER_FMK(MCBSP,RCR,RFIG,rfig)\
|_PER_FMK(MCBSP,RCR,RDATDLY,rdatdly)\
|_PER_FMK(MCBSP,RCR,RFRLEN1,rfrlen1)\
|_PER_FMK(MCBSP,RCR,RWDLEN1,rwdlen1)\
|_PER_FMK(MCBSP,RCR,RWDREVRS,rwdrevrs)\
)
#endif
#if (!C11_SUPPORT && !C64_SUPPORT)
#define MCBSP_RCR_DEFAULT (Uint32)(\
_PER_FDEFAULT(MCBSP,RCR,RPHASE)\
|_PER_FDEFAULT(MCBSP,RCR,RFRLEN2)\
|_PER_FDEFAULT(MCBSP,RCR,RWDLEN2)\
|_PER_FDEFAULT(MCBSP,RCR,RCOMPAND)\
|_PER_FDEFAULT(MCBSP,RCR,RFIG)\
|_PER_FDEFAULT(MCBSP,RCR,RDATDLY)\
|_PER_FDEFAULT(MCBSP,RCR,RFRLEN1)\
|_PER_FDEFAULT(MCBSP,RCR,RWDLEN1)\
)
#define MCBSP_RCR_RMK(rphase,rfrlen2,rwdlen2,rcompand,rfig,\
rdatdly,rfrlen1,rwdlen1) (Uint32)(\
_PER_FMK(MCBSP,RCR,RPHASE,rphase)\
|_PER_FMK(MCBSP,RCR,RFRLEN2,rfrlen2)\
|_PER_FMK(MCBSP,RCR,RWDLEN2,rwdlen2)\
|_PER_FMK(MCBSP,RCR,RCOMPAND,rcompand)\
|_PER_FMK(MCBSP,RCR,RFIG,rfig)\
|_PER_FMK(MCBSP,RCR,RDATDLY,rdatdly)\
|_PER_FMK(MCBSP,RCR,RFRLEN1,rfrlen1)\
|_PER_FMK(MCBSP,RCR,RWDLEN1,rwdlen1)\
)
#endif
#define _MCBSP_RCR_FGET(N,FIELD)\
_PER_FGET(_MCBSP_RCR##N##_ADDR,MCBSP,RCR,##FIELD)
#define _MCBSP_RCR_FSET(N,FIELD,field)\
_PER_FSET(_MCBSP_RCR##N##_ADDR,MCBSP,RCR,##FIELD,field)
#define _MCBSP_RCR_FSETS(N,FIELD,SYM)\
_PER_FSETS(_MCBSP_RCR##N##_ADDR,MCBSP,RCR,##FIELD,##SYM)
#define _MCBSP_RCR0_FGET(FIELD) _MCBSP_RCR_FGET(0,##FIELD)
#define _MCBSP_RCR1_FGET(FIELD) _MCBSP_RCR_FGET(1,##FIELD)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_RCR2_FGET(FIELD) _MCBSP_RCR_FGET(2,##FIELD)
#endif
#define _MCBSP_RCR0_FSET(FIELD,f) _MCBSP_RCR_FSET(0,##FIELD,f)
#define _MCBSP_RCR1_FSET(FIELD,f) _MCBSP_RCR_FSET(1,##FIELD,f)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_RCR2_FSET(FIELD,f) _MCBSP_RCR_FSET(2,##FIELD,f)
#endif
#define _MCBSP_RCR0_FSETS(FIELD,SYM) _MCBSP_RCR_FSETS(0,##FIELD,##SYM)
#define _MCBSP_RCR1_FSETS(FIELD,SYM) _MCBSP_RCR_FSETS(1,##FIELD,##SYM)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_RCR2_FSETS(FIELD,SYM) _MCBSP_RCR_FSETS(2,##FIELD,##SYM)
#endif
/******************************************************************************\
* _____________________
* | |
* | X C R |
* |___________________|
*
* XCR0 - serial port 0 transmit control register
* XCR1 - serial port 1 transmit control register
* XCR2 - serial port 2 transmit control register (1)
*
* (1) only supported on devices with three serial ports
*
* FIELDS (msb -> lsb)
* (rw) XPHASE
* (rw) XFRLEN2
* (rw) XWDLEN2
* (rw) XCOMPAND
* (rw) XFIG
* (rw) XDATDLY
* (rw) XFRLEN1
* (rw) XWDLEN1
* (rw) XWDREVRS (2)
*
* (2) - C11_SUPPORT /C64_SUPPORT only
*
\******************************************************************************/
#define _MCBSP_XCR_OFFSET 4
#define _MCBSP_XCR0_ADDR 0x01840010u
#define _MCBSP_XCR1_ADDR 0x01900010u
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_XCR2_ADDR 0x01A40010u
#endif
#define _MCBSP_XCR_XPHASE_MASK 0x80000000u
#define _MCBSP_XCR_XPHASE_SHIFT 0x0000001Fu
#define MCBSP_XCR_XPHASE_DEFAULT 0x00000000u
#define MCBSP_XCR_XPHASE_OF(x) _VALUEOF(x)
#define MCBSP_XCR_XPHASE_SINGLE 0x00000000u
#define MCBSP_XCR_XPHASE_DUAL 0x00000001u
#define _MCBSP_XCR_XFRLEN2_MASK 0x7F000000u
#define _MCBSP_XCR_XFRLEN2_SHIFT 0x00000018u
#define MCBSP_XCR_XFRLEN2_DEFAULT 0x00000000u
#define MCBSP_XCR_XFRLEN2_OF(x) _VALUEOF(x)
#define _MCBSP_XCR_XWDLEN2_MASK 0x00E00000u
#define _MCBSP_XCR_XWDLEN2_SHIFT 0x00000015u
#define MCBSP_XCR_XWDLEN2_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDLEN2_OF(x) _VALUEOF(x)
#define MCBSP_XCR_XWDLEN2_8BIT 0x00000000u
#define MCBSP_XCR_XWDLEN2_12BIT 0x00000001u
#define MCBSP_XCR_XWDLEN2_16BIT 0x00000002u
#define MCBSP_XCR_XWDLEN2_20BIT 0x00000003u
#define MCBSP_XCR_XWDLEN2_24BIT 0x00000004u
#define MCBSP_XCR_XWDLEN2_32BIT 0x00000005u
#define _MCBSP_XCR_XCOMPAND_MASK 0x00180000u
#define _MCBSP_XCR_XCOMPAND_SHIFT 0x00000013u
#define MCBSP_XCR_XCOMPAND_DEFAULT 0x00000000u
#define MCBSP_XCR_XCOMPAND_OF(x) _VALUEOF(x)
#define MCBSP_XCR_XCOMPAND_MSB 0x00000000u
#define MCBSP_XCR_XCOMPAND_8BITLSB 0x00000001u
#define MCBSP_XCR_XCOMPAND_ULAW 0x00000002u
#define MCBSP_XCR_XCOMPAND_ALAW 0x00000003u
#define _MCBSP_XCR_XFIG_MASK 0x00040000u
#define _MCBSP_XCR_XFIG_SHIFT 0x00000012u
#define MCBSP_XCR_XFIG_DEFAULT 0x00000000u
#define MCBSP_XCR_XFIG_OF(x) _VALUEOF(x)
#define MCBSP_XCR_XFIG_NO 0x00000000u
#define MCBSP_XCR_XFIG_YES 0x00000001u
#define _MCBSP_XCR_XDATDLY_MASK 0x00030000u
#define _MCBSP_XCR_XDATDLY_SHIFT 0x00000010u
#define MCBSP_XCR_XDATDLY_DEFAULT 0x00000000u
#define MCBSP_XCR_XDATDLY_OF(x) _VALUEOF(x)
#define MCBSP_XCR_XDATDLY_0BIT 0x00000000u
#define MCBSP_XCR_XDATDLY_1BIT 0x00000001u
#define MCBSP_XCR_XDATDLY_2BIT 0x00000002u
#define _MCBSP_XCR_XFRLEN1_MASK 0x00007F00u
#define _MCBSP_XCR_XFRLEN1_SHIFT 0x00000008u
#define MCBSP_XCR_XFRLEN1_DEFAULT 0x00000000u
#define MCBSP_XCR_XFRLEN1_OF(x) _VALUEOF(x)
#define _MCBSP_XCR_XWDLEN1_MASK 0x000000E0u
#define _MCBSP_XCR_XWDLEN1_SHIFT 0x00000005u
#define MCBSP_XCR_XWDLEN1_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDLEN1_OF(x) _VALUEOF(x)
#define MCBSP_XCR_XWDLEN1_8BIT 0x00000000u
#define MCBSP_XCR_XWDLEN1_12BIT 0x00000001u
#define MCBSP_XCR_XWDLEN1_16BIT 0x00000002u
#define MCBSP_XCR_XWDLEN1_20BIT 0x00000003u
#define MCBSP_XCR_XWDLEN1_24BIT 0x00000004u
#define MCBSP_XCR_XWDLEN1_32BIT 0x00000005u
#if (C11_SUPPORT || C64_SUPPORT)
#define _MCBSP_XCR_XWDREVRS_MASK 0x00000010u
#define _MCBSP_XCR_XWDREVRS_SHIFT 0x00000004u
#define MCBSP_XCR_XWDREVRS_DEFAULT 0x00000000u
#define MCBSP_XCR_XWDREVRS_OF(x) _VALUEOF(x)
#define MCBSP_XCR_XWDREVRS_DISABLE 0x00000000u
#define MCBSP_XCR_XWDREVRS_ENABLE 0x00000001u
#endif
#define MCBSP_XCR_OF(x) _VALUEOF(x)
#if (C11_SUPPORT || C64_SUPPORT)
#define MCBSP_XCR_DEFAULT (Uint32)(\
_PER_FDEFAULT(MCBSP,XCR,XPHASE)\
|_PER_FDEFAULT(MCBSP,XCR,XFRLEN2)\
|_PER_FDEFAULT(MCBSP,XCR,XWDLEN2)\
|_PER_FDEFAULT(MCBSP,XCR,XCOMPAND)\
|_PER_FDEFAULT(MCBSP,XCR,XFIG)\
|_PER_FDEFAULT(MCBSP,XCR,XDATDLY)\
|_PER_FDEFAULT(MCBSP,XCR,XFRLEN1)\
|_PER_FDEFAULT(MCBSP,XCR,XWDLEN1)\
|_PER_FDEFAULT(MCBSP,XCR,XWDREVRS)\
)
#define MCBSP_XCR_RMK(xphase,xfrlen2,xwdlen2,xcompand,xfig,\
xdatdly,xfrlen1,xwdlen1,xwdrevrs) (Uint32)(\
_PER_FMK(MCBSP,XCR,XPHASE,xphase)\
|_PER_FMK(MCBSP,XCR,XFRLEN2,xfrlen2)\
|_PER_FMK(MCBSP,XCR,XWDLEN2,xwdlen2)\
|_PER_FMK(MCBSP,XCR,XCOMPAND,xcompand)\
|_PER_FMK(MCBSP,XCR,XFIG,xfig)\
|_PER_FMK(MCBSP,XCR,XDATDLY,xdatdly)\
|_PER_FMK(MCBSP,XCR,XFRLEN1,xfrlen1)\
|_PER_FMK(MCBSP,XCR,XWDLEN1,xwdlen1)\
|_PER_FMK(MCBSP,XCR,XWDREVRS,xwdrevrs)\
)
#endif
#if (!C11_SUPPORT && !C64_SUPPORT)
#define MCBSP_XCR_DEFAULT (Uint32)(\
_PER_FDEFAULT(MCBSP,XCR,XPHASE)\
|_PER_FDEFAULT(MCBSP,XCR,XFRLEN2)\
|_PER_FDEFAULT(MCBSP,XCR,XWDLEN2)\
|_PER_FDEFAULT(MCBSP,XCR,XCOMPAND)\
|_PER_FDEFAULT(MCBSP,XCR,XFIG)\
|_PER_FDEFAULT(MCBSP,XCR,XDATDLY)\
|_PER_FDEFAULT(MCBSP,XCR,XFRLEN1)\
|_PER_FDEFAULT(MCBSP,XCR,XWDLEN1)\
)
#define MCBSP_XCR_RMK(xphase,xfrlen2,xwdlen2,xcompand,xfig,\
xdatdly,xfrlen1,xwdlen1) (Uint32)(\
_PER_FMK(MCBSP,XCR,XPHASE,xphase)\
|_PER_FMK(MCBSP,XCR,XFRLEN2,xfrlen2)\
|_PER_FMK(MCBSP,XCR,XWDLEN2,xwdlen2)\
|_PER_FMK(MCBSP,XCR,XCOMPAND,xcompand)\
|_PER_FMK(MCBSP,XCR,XFIG,xfig)\
|_PER_FMK(MCBSP,XCR,XDATDLY,xdatdly)\
|_PER_FMK(MCBSP,XCR,XFRLEN1,xfrlen1)\
|_PER_FMK(MCBSP,XCR,XWDLEN1,xwdlen1)\
)
#endif
#define _MCBSP_XCR_FGET(N,FIELD)\
_PER_FGET(_MCBSP_XCR##N##_ADDR,MCBSP,XCR,##FIELD)
#define _MCBSP_XCR_FSET(N,FIELD,field)\
_PER_FSET(_MCBSP_XCR##N##_ADDR,MCBSP,XCR,##FIELD,field)
#define _MCBSP_XCR_FSETS(N,FIELD,SYM)\
_PER_FSETS(_MCBSP_XCR##N##_ADDR,MCBSP,XCR,##FIELD,##SYM)
#define _MCBSP_XCR0_FGET(FIELD) _MCBSP_XCR_FGET(0,##FIELD)
#define _MCBSP_XCR1_FGET(FIELD) _MCBSP_XCR_FGET(1,##FIELD)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_XCR2_FGET(FIELD) _MCBSP_XCR_FGET(2,##FIELD)
#endif
#define _MCBSP_XCR0_FSET(FIELD,f) _MCBSP_XCR_FSET(0,##FIELD,f)
#define _MCBSP_XCR1_FSET(FIELD,f) _MCBSP_XCR_FSET(1,##FIELD,f)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_XCR2_FSET(FIELD,f) _MCBSP_XCR_FSET(2,##FIELD,f)
#endif
#define _MCBSP_XCR0_FSETS(FIELD,SYM) _MCBSP_XCR_FSETS(0,##FIELD,##SYM)
#define _MCBSP_XCR1_FSETS(FIELD,SYM) _MCBSP_XCR_FSETS(1,##FIELD,##SYM)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_XCR2_FSETS(FIELD,SYM) _MCBSP_XCR_FSETS(2,##FIELD,##SYM)
#endif
/******************************************************************************\
* _____________________
* | |
* | S R G R |
* |___________________|
*
* SRGR0 - serial port 0 sample rate generator register
* SRGR1 - serial port 1 sample rate generator register
* SRGR2 - serial port 2 sample rate generator register (1)
*
* (1) only supported on devices with three serial ports
*
* FIELDS (msb -> lsb)
* (rw) GSYNC
* (rw) CLKSP
* (rw) CLKSM
* (rw) FSGM
* (rw) FPER
* (rw) FWID
* (rw) CLKGDV
*
\******************************************************************************/
#define _MCBSP_SRGR_OFFSET 5
#define _MCBSP_SRGR0_ADDR 0x018C0014u
#define _MCBSP_SRGR1_ADDR 0x01900014u
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_SRGR2_ADDR 0x01A40014u
#endif
#define _MCBSP_SRGR_GSYNC_MASK 0x80000000u
#define _MCBSP_SRGR_GSYNC_SHIFT 0x0000001Fu
#define MCBSP_SRGR_GSYNC_DEFAULT 0x00000000u
#define MCBSP_SRGR_GSYNC_OF(x) _VALUEOF(x)
#define MCBSP_SRGR_GSYNC_FREE 0x00000000u
#define MCBSP_SRGR_GSYNC_SYNC 0x00000001u
#define _MCBSP_SRGR_CLKSP_MASK 0x40000000u
#define _MCBSP_SRGR_CLKSP_SHIFT 0x0000001Eu
#define MCBSP_SRGR_CLKSP_DEFAULT 0x00000000u
#define MCBSP_SRGR_CLKSP_OF(x) _VALUEOF(x)
#define MCBSP_SRGR_CLKSP_RISING 0x00000000u
#define MCBSP_SRGR_CLKSP_FALLING 0x00000001u
#define _MCBSP_SRGR_CLKSM_MASK 0x20000000u
#define _MCBSP_SRGR_CLKSM_SHIFT 0x0000001Du
#define MCBSP_SRGR_CLKSM_DEFAULT 0x00000001u
#define MCBSP_SRGR_CLKSM_OF(x) _VALUEOF(x)
#define MCBSP_SRGR_CLKSM_CLKS 0x00000000u
#define MCBSP_SRGR_CLKSM_INTERNAL 0x00000001u
#define _MCBSP_SRGR_FSGM_MASK 0x10000000u
#define _MCBSP_SRGR_FSGM_SHIFT 0x0000001Cu
#define MCBSP_SRGR_FSGM_DEFAULT 0x00000000u
#define MCBSP_SRGR_FSGM_OF(x) _VALUEOF(x)
#define MCBSP_SRGR_FSGM_DXR2XSR 0x00000000u
#define MCBSP_SRGR_FSGM_FSG 0x00000001u
#define _MCBSP_SRGR_FPER_MASK 0x0FFF0000u
#define _MCBSP_SRGR_FPER_SHIFT 0x00000010u
#define MCBSP_SRGR_FPER_DEFAULT 0x00000000u
#define MCBSP_SRGR_FPER_OF(x) _VALUEOF(x)
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