📄 csl_mcbsphal.h
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/******************************************************************************\
* Copyright (C) 1999-2001 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_mcbsphal.h
* DATE CREATED.. 06/12/1999
* LAST MODIFIED. 10/02/2001
* - 6713 device addition
*------------------------------------------------------------------------------
* REGISTERS
*
* DRR0 - serial port 0 data receive register
* DRR1 - serial port 1 data receive register
* DRR2 - serial port 2 data receive register (1)
* DXR0 - serial port 0 data transmit register
* DXR1 - serial port 1 data transmit register
* DXR2 - serial port 2 data transmit register (1)
* SPCR0 - serial port 0 control register
* SPCR1 - serial port 1 control register
* SPCR2 - serial port 2 control register (1)
* RCR0 - serial port 0 receive control register
* RCR1 - serial port 1 receive control register
* RCR2 - serial port 2 receive control register (1)
* XCR0 - serial port 0 transmit control register
* XCR1 - serial port 1 transmit control register
* XCR2 - serial port 2 transmit control register (1)
* SRGR0 - serial port 0 sample rate generator register
* SRGR1 - serial port 1 sample rate generator register
* SRGR2 - serial port 2 sample rate generator register (1)
* MCR0 - serial port 0 multichannel control register
* MCR1 - serial port 1 multichannel control register
* MCR2 - serial port 2 multichannel control register (1)
* RCER0 - serial port 0 receive channel enable register
* RCER1 - serial port 1 receive channel enable register
* RCER2 - serial port 2 receive channel enable register (1)
* XCER0 - serial port 0 transmit channel enable register
* XCER1 - serial port 1 transmit channel enable register
* XCER2 - serial port 2 transmit channel enable register (1)
* RCERE00 - serial port 0 Enhanced receive channel enable register 0 (2)
* RCERE01 - serial port 1 Enhanced receive channel enable register 0 (2)
* RCERE02 - serial port 2 Enhanced receive channel enable register 0 (2)
* RCERE10 - serial port 0 Enhanced receive channel enable register 1 (2)
* RCERE11 - serial port 1 Enhanced receive channel enable register 1 (2)
* RCERE12 - serial port 2 Enhanced receive channel enable register 1 (2)
* RCERE20 - serial port 0 Enhanced receive channel enable register 2 (2)
* RCERE21 - serial port 1 Enhanced receive channel enable register 2 (2)
* RCERE22 - serial port 2 Enhanced receive channel enable register 2 (2)
* RCERE30 - serial port 0 Enhanced receive channel enable register 3 (2)
* RCERE31 - serial port 1 Enhanced receive channel enable register 3 (2)
* RCERE32 - serial port 2 Enhanced receive channel enable register 3 (2)
* XCERE00 - serial port 0 Enhanced transmit channel enable register 0 (2)
* XCERE01 - serial port 1 Enhanced transmit channel enable register 0 (2)
* XCERE02 - serial port 2 Enhanced transmit channel enable register 0 (2)
* XCERE10 - serial port 0 Enhanced transmit channel enable register 1 (2)
* XCERE11 - serial port 1 Enhanced transmit channel enable register 1 (2)
* XCERE12 - serial port 2 Enhanced transmit channel enable register 1 (2)
* XCERE20 - serial port 0 Enhanced transmit channel enable register 2 (2)
* XCERE21 - serial port 1 Enhanced transmit channel enable register 2 (2)
* XCERE22 - serial port 2 Enhanced transmit channel enable register 2 (2)
* XCERE30 - serial port 0 Enhanced transmit channel enable register 3 (2)
* XCERE31 - serial port 1 Enhanced transmit channel enable register 3 (2)
* XCERE32 - serial port 2 Enhanced transmit channel enable register 3 (2)
* PCR0 - serial port 0 pin control register
* PCR1 - serial port 1 pin control register
* PCR2 - serial port 2 pin control register (1)
*
* (1) only supported on devices with three serial ports
* (2) supported by C64x devices (RCERx replaced by RCERE0x, XCERx replaced by XCERE0x)
*
\******************************************************************************/
#ifndef _CSL_MCBSPHAL_H_
#define _CSL_MCBSPHAL_H_
#include <csl_stdinc.h>
#include <csl_chip.h>
#if (MCBSP_SUPPORT)
/******************************************************************************\
* MISC section
\******************************************************************************/
#if (CHIP_6202|CHIP_6203|CHIP_6414|CHIP_6415|CHIP_6416)
#define _MCBSP_PORT_CNT 3
#define _MCBSP_BASE_PORT0 0x018C0000u
#define _MCBSP_BASE_PORT1 0x01900000u
#define _MCBSP_BASE_PORT2 0x01A40000u
#else
#define _MCBSP_PORT_CNT 2
#define _MCBSP_BASE_PORT0 0x018C0000u
#define _MCBSP_BASE_PORT1 0x01900000u
#endif
/******************************************************************************\
* module level register/field access macros
\******************************************************************************/
/* ----------------- */
/* FIELD MAKE MACROS */
/* ----------------- */
#define MCBSP_FMK(REG,FIELD,x)\
_PER_FMK(MCBSP,##REG,##FIELD,x)
#define MCBSP_FMKS(REG,FIELD,SYM)\
_PER_FMKS(MCBSP,##REG,##FIELD,##SYM)
/* -------------------------------- */
/* RAW REGISTER/FIELD ACCESS MACROS */
/* -------------------------------- */
#define MCBSP_ADDR(REG)\
_MCBSP_##REG##_ADDR
#define MCBSP_RGET(REG)\
_PER_RGET(_MCBSP_##REG##_ADDR,MCBSP,##REG)
#define MCBSP_RSET(REG,x)\
_PER_RSET(_MCBSP_##REG##_ADDR,MCBSP,##REG,x)
#define MCBSP_FGET(REG,FIELD)\
_MCBSP_##REG##_FGET(##FIELD)
#define MCBSP_FSET(REG,FIELD,x)\
_MCBSP_##REG##_FSET(##FIELD,##x)
#define MCBSP_FSETS(REG,FIELD,SYM)\
_MCBSP_##REG##_FSETS(##FIELD,##SYM)
/* ------------------------------------------ */
/* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */
/* ------------------------------------------ */
#define MCBSP_RGETA(addr,REG)\
_PER_RGET(addr,MCBSP,##REG)
#define MCBSP_RSETA(addr,REG,x)\
_PER_RSET(addr,MCBSP,##REG,x)
#define MCBSP_FGETA(addr,REG,FIELD)\
_PER_FGET(addr,MCBSP,##REG,##FIELD)
#define MCBSP_FSETA(addr,REG,FIELD,x)\
_PER_FSET(addr,MCBSP,##REG,##FIELD,x)
#define MCBSP_FSETSA(addr,REG,FIELD,SYM)\
_PER_FSETS(addr,MCBSP,##REG,##FIELD,##SYM)
/* ----------------------------------------- */
/* HANDLE BASED REGISTER/FIELD ACCESS MACROS */
/* ----------------------------------------- */
#define MCBSP_ADDRH(h,REG)\
(Uint32)(&((h)->baseAddr[_MCBSP_##REG##_OFFSET]))
#define MCBSP_RGETH(h,REG)\
MCBSP_RGETA(MCBSP_ADDRH(h,##REG),##REG)
#define MCBSP_RSETH(h,REG,x)\
MCBSP_RSETA(MCBSP_ADDRH(h,##REG),##REG,x)
#define MCBSP_FGETH(h,REG,FIELD)\
MCBSP_FGETA(MCBSP_ADDRH(h,##REG),##REG,##FIELD)
#define MCBSP_FSETH(h,REG,FIELD,x)\
MCBSP_FSETA(MCBSP_ADDRH(h,##REG),##REG,##FIELD,x)
#define MCBSP_FSETSH(h,REG,FIELD,SYM)\
MCBSP_FSETSA(MCBSP_ADDRH(h,##REG),##REG,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | D R R |
* |___________________|
*
* DRR0 - serial port 0 data receive register
* DRR1 - serial port 1 data receive register
* DRR2 - serial port 2 data receive register (1)
*
* (1) only supported on devices with three serial ports
*
* FIELDS (msb -> lsb)
* (r) DR
*
\******************************************************************************/
#define _MCBSP_DRR_OFFSET 0
#if (C11_SUPPORT || C64_SUPPORT)
#define _MCBSP_DRR0_ADDR 0x30000000u
#define _MCBSP_DRR1_ADDR 0x34000000u
#else
#define _MCBSP_DRR0_ADDR 0x018C0000u
#define _MCBSP_DRR1_ADDR 0x01900000u
#endif
#if (_MCBSP_PORT_CNT==3 && (CHIP_6202 || CHIP_6203 ) )
#define _MCBSP_DRR2_ADDR 0x01A40000u
#endif
#if (_MCBSP_PORT_CNT==3 && (CHIP_6414 || CHIP_6415 || CHIP_6416))
#define _MCBSP_DRR2_ADDR 0x38000000u
#endif
#define _MCBSP_DRR_DR_MASK 0xFFFFFFFFu
#define _MCBSP_DRR_DR_SHIFT 0x00000000u
#define MCBSP_DRR_DR_DEFAULT 0x00000000u
#define MCBSP_DRR_DR_OF(x) _VALUEOF(x)
#define MCBSP_DRR_OF(x) _VALUEOF(x)
#define MCBSP_DRR_DEFAULT (Uint32)(\
_PER_FDEFAULT(MCBSP,DRR,DR)\
)
#define MCBSP_DRR_RMK(dr) (Uint32)(\
_PER_FMK(MCBSP,DRR,DR,dr)\
)
#define _MCBSP_DRR_FGET(N,FIELD)\
_PER_FGET(_MCBSP_DRR##N##_ADDR,MCBSP,DRR,##FIELD)
#define _MCBSP_DRR_FSET(N,FIELD,field)\
_PER_FSET(_MCBSP_DRR##N##_ADDR,MCBSP,DRR,##FIELD,field)
#define _MCBSP_DRR_FSETS(N,FIELD,SYM)\
_PER_FSETS(_MCBSP_DRR##N##_ADDR,MCBSP,DRR,##FIELD,##SYM)
#define _MCBSP_DRR0_FGET(FIELD) _MCBSP_DRR_FGET(0,##FIELD)
#define _MCBSP_DRR1_FGET(FIELD) _MCBSP_DRR_FGET(1,##FIELD)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_DRR2_FGET(FIELD) _MCBSP_DRR_FGET(2,##FIELD)
#endif
#define _MCBSP_DRR0_FSET(FIELD,f) _MCBSP_DRR_FSET(0,##FIELD,f)
#define _MCBSP_DRR1_FSET(FIELD,f) _MCBSP_DRR_FSET(1,##FIELD,f)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_DRR2_FSET(FIELD,f) _MCBSP_DRR_FSET(2,##FIELD,f)
#endif
#define _MCBSP_DRR0_FSETS(FIELD,SYM) _MCBSP_DRR_FSETS(0,##FIELD,##SYM)
#define _MCBSP_DRR1_FSETS(FIELD,SYM) _MCBSP_DRR_FSETS(1,##FIELD,##SYM)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_DRR2_FSETS(FIELD,SYM) _MCBSP_DRR_FSETS(2,##FIELD,##SYM)
#endif
/******************************************************************************\
* _____________________
* | |
* | D X R |
* |___________________|
*
* DXR0 - serial port 0 data transmit register
* DXR1 - serial port 1 data transmit register
* DXR2 - serial port 2 data transmit register (1)
*
* (1) only supported on devices with three serial ports
*
* FIELDS (msb -> lsb)
* (w) DX
*
\******************************************************************************/
#define _MCBSP_DXR_OFFSET 1
#if (C11_SUPPORT || C64_SUPPORT)
#define _MCBSP_DXR0_ADDR 0x30000000u
#define _MCBSP_DXR1_ADDR 0x34000000u
#else
#define _MCBSP_DXR0_ADDR 0x018C0004u
#define _MCBSP_DXR1_ADDR 0x01900004u
#endif
#if (_MCBSP_PORT_CNT==3 && (CHIP_6202 || CHIP_6203) )
#define _MCBSP_DXR2_ADDR 0x01A40004u
#endif
#if (_MCBSP_PORT_CNT==3 && (CHIP_6414 || CHIP_6415 || CHIP_6416))
#define _MCBSP_DXR2_ADDR 0x38000000u
#endif
#define _MCBSP_DXR_DX_MASK 0xFFFFFFFFu
#define _MCBSP_DXR_DX_SHIFT 0x00000000u
#define MCBSP_DXR_DX_DEFAULT 0x00000000u
#define MCBSP_DXR_DX_OF(x) _VALUEOF(x)
#define MCBSP_DXR_OF(x) _VALUEOF(x)
#define MCBSP_DXR_DEFAULT (Uint32)(\
_PER_FDEFAULT(MCBSP,DXR,DX)\
)
#define MCBSP_DXR_RMK(dr) (Uint32)(\
_PER_FMK(MCBSP,DXR,DX,dr)\
)
#define _MCBSP_DXR_FGET(N,FIELD)\
_PER_FGET(_MCBSP_DXR##N##_ADDR,MCBSP,DXR,##FIELD)
#define _MCBSP_DXR_FSET(N,FIELD,field)\
_PER_FSET(_MCBSP_DXR##N##_ADDR,MCBSP,DXR,##FIELD,field)
#define _MCBSP_DXR_FSETS(N,FIELD,SYM)\
_PER_FSETS(_MCBSP_DXR##N##_ADDR,MCBSP,DXR,##FIELD,##SYM)
#define _MCBSP_DXR0_FGET(FIELD) _MCBSP_DXR_FGET(0,##FIELD)
#define _MCBSP_DXR1_FGET(FIELD) _MCBSP_DXR_FGET(1,##FIELD)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_DXR2_FGET(FIELD) _MCBSP_DXR_FGET(2,##FIELD)
#endif
#define _MCBSP_DXR0_FSET(FIELD,f) _MCBSP_DXR_FSET(0,##FIELD,f)
#define _MCBSP_DXR1_FSET(FIELD,f) _MCBSP_DXR_FSET(1,##FIELD,f)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_DXR2_FSET(FIELD,f) _MCBSP_DXR_FSET(2,##FIELD,f)
#endif
#define _MCBSP_DXR0_FSETS(FIELD,SYM) _MCBSP_DXR_FSETS(0,##FIELD,##SYM)
#define _MCBSP_DXR1_FSETS(FIELD,SYM) _MCBSP_DXR_FSETS(1,##FIELD,##SYM)
#if (_MCBSP_PORT_CNT==3)
#define _MCBSP_DXR2_FSETS(FIELD,SYM) _MCBSP_DXR_FSETS(2,##FIELD,##SYM)
#endif
/******************************************************************************\
* _____________________
* | |
* | S P C R |
* |___________________|
*
* SPCR0 - serial port 0 control register
* SPCR1 - serial port 1 control register
* SPCR2 - serial port 2 control register (1)
*
* (1) only supported on devices with three serial ports
*
* FIELDS (msb -> lsb)
* (rw) FREE (2)
* (rw) SOFT (2)
* (rw) FRST
* (rw) GRST
* (rw) XINTM
* (rw) XSYNCERR
* (r) XEMPTY
* (r) XRDY
* (rw) XRST
* (rw) DLB
* (rw) RJUST
* (rw) CLKSTP
* (rw) DXENA (2)
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