📄 c62.h62
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;
; Copyright 2003 by Texas Instruments Incorporated.
; All rights reserved. Property of Texas Instruments Incorporated.
; Restricted rights to use, duplicate or disclose this code are
; granted through contract.
;
;
; "@(#) DSP/BIOS 4.90.270 12-18-03 (barracuda-o04)"
;
; ======== c62.h62 ========
; Assembly language c62 macros
;
;
.if ($isdefed("C62_") = 0) ; prevent multiple includes
C62_ .set 1
.include hwi.h62
.if .TMS320C6400
.include c64.h64
.endif
;
; Symbol and constant definitions
;
.asg a15, FP ; Frame Pointer
.asg b14, DP ; Data Page Register
.asg b15, SP ; Stack Pointer
;
; CSR bits
;
GIE .set 0x0001 ; Global Interrupt Enable bit in CSR
SAT .set 0x0200 ; SAT bit in CSR
;
; Values used for CCMASK in HWI_enter/HWI_exit.
;
C62_PCC_DISABLE .set 0x0000 ; Program Cache Control code
C62_PCC_ENABLE .set 0x0040 ; Program Cache Control code
C62_PCC_FREEZE .set 0x0060 ; Program Cache Control code
C62_PCC_BYPASS .set 0x0080 ; Program Cache Control code
C62_CCFIELDS .set 0x00fc ; Cache Control field mask
;
; Register bitmap position definitions used below
;
C62_ra0 .set 0
C62_ra1 .set 1
C62_ra2 .set 2
C62_ra3 .set 3
C62_ra4 .set 4
C62_ra5 .set 5
C62_ra6 .set 6
C62_ra7 .set 7
C62_ra8 .set 8
C62_ra9 .set 9
C62_ra10 .set 10
C62_ra11 .set 11
C62_ra12 .set 12
C62_ra13 .set 13
C62_ra14 .set 14
C62_ra15 .set 15
C62_rb0 .set 16
C62_rb1 .set 17
C62_rb2 .set 18
C62_rb3 .set 19
C62_rb4 .set 20
C62_rb5 .set 21
C62_rb6 .set 22
C62_rb7 .set 23
C62_rb8 .set 24
C62_rb9 .set 25
C62_rb10 .set 26
C62_rb11 .set 27
C62_rb12 .set 28
C62_rb13 .set 29
C62_rb14 .set 30
C62_rb15 .set 31
C62_ramr .set 0
C62_rcsr .set 1
C62_rier .set 2
C62_rist .set 3
C62_rirp .set 4
C62_rnrp .set 5
;
; Definitions for C62_xTEMPS
;
C62_A0 .set 1 << C62_ra0
C62_A1 .set 1 << C62_ra1
C62_A2 .set 1 << C62_ra2
C62_A3 .set 1 << C62_ra3
C62_A4 .set 1 << C62_ra4
C62_A5 .set 1 << C62_ra5
C62_A6 .set 1 << C62_ra6
C62_A7 .set 1 << C62_ra7
C62_A8 .set 1 << C62_ra8
C62_A9 .set 1 << C62_ra9
C62_A10 .set 1 << C62_ra10
C62_A11 .set 1 << C62_ra11
C62_A12 .set 1 << C62_ra12
C62_A13 .set 1 << C62_ra13
C62_A14 .set 1 << C62_ra14
C62_A15 .set 1 << C62_ra15
C62_B0 .set 1 << C62_rb0
C62_B1 .set 1 << C62_rb1
C62_B2 .set 1 << C62_rb2
C62_B3 .set 1 << C62_rb3
C62_B4 .set 1 << C62_rb4
C62_B5 .set 1 << C62_rb5
C62_B6 .set 1 << C62_rb6
C62_B7 .set 1 << C62_rb7
C62_B8 .set 1 << C62_rb8
C62_B9 .set 1 << C62_rb9
C62_B10 .set 1 << C62_rb10
C62_B11 .set 1 << C62_rb11
C62_B12 .set 1 << C62_rb12
C62_B13 .set 1 << C62_rb13
C62_B14 .set 1 << C62_rb14
C62_B15 .set 1 << C62_rb15
C62_AMR .set 1 << C62_ramr ; Addressing mode register
C62_CSR .set 1 << C62_rcsr ; Control status register
C62_IER .set 1 << C62_rier ; Interrupt enable register
C62_IST .set 1 << C62_rist ; Interrupt service table pointer
C62_IRP .set 1 << C62_rirp ; Interrupt return pointer
C62_NRP .set 1 << C62_rnrp ; Non-maskable int. return pointer
;
; Interrupt Enable Register (and Interrupt Flag Register) bit definitions
;
C62_NMIE .set 1 << 1 ; Non-maskable Interrupt Enable bit
C62_IE2 .set 1 << 2 ; Reserved Interrupt 2 Enable
C62_IE3 .set 1 << 3 ; Reserved Interrupt 3 Enable
C62_IE4 .set 1 << 4 ; Interrupt Enable 4
C62_IE5 .set 1 << 5 ; Interrupt Enable 5
C62_IE6 .set 1 << 6 ; Interrupt Enable 6
C62_IE7 .set 1 << 7 ; Interrupt Enable 7
C62_IE8 .set 1 << 8 ; Interrupt Enable 8
C62_IE9 .set 1 << 9 ; Interrupt Enable 9
C62_IE10 .set 1 << 10 ; Interrupt Enable 10
C62_IE11 .set 1 << 11 ; Interrupt Enable 11
C62_IE12 .set 1 << 12 ; Interrupt Enable 12
C62_IE13 .set 1 << 13 ; Interrupt Enable 13
C62_IE14 .set 1 << 14 ; Interrupt Enable 14
C62_IE15 .set 1 << 15 ; Interrupt Enable 15
;
; Masks for ISR registers saved and restored internally
;
C62_ISRAB .set C62_A0 | C62_A1 | C62_A2 | C62_A3 | C62_B0 | C62_B1 | C62_B2 | C62_B3 | C62_B14
C62_ISRC .set C62_AMR | C62_IRP | C62_IER
;
; Register combinations
;
C62_ATEMPSLO .set C62_A0 | C62_A1 | C62_A2 | C62_A3 | C62_A4
C62_ATEMPSHI .set C62_A5 | C62_A6 | C62_A7 | C62_A8 | C62_A9
C62_ATEMPS .set C62_ATEMPSLO | C62_ATEMPSHI
C62_BTEMPSLO .set C62_B0 | C62_B1 | C62_B2 | C62_B3 | C62_B4
C62_BTEMPSHI .set C62_B5 | C62_B6 | C62_B7 | C62_B8 | C62_B9
C62_BTEMPS .set C62_BTEMPSLO | C62_BTEMPSHI
C62_CTEMPS .set C62_AMR
C62_ABTEMPS .set C62_ATEMPS | C62_BTEMPS
;
;# ======== C62_set ========
;
; This macro conditionally sets bits in two masks corresponding to a passed
; list of registers. The first parameter is the name of the AB register
; mask, and the second is the name of the control register mask. This macro
; is typically used to prior to calls to C62_save and C62_restore.
;
; C62_set ABMASK, CMASK
;
; ABMASK - Mask of A and B registers included in the list
; CMASK - Mask of control registers included in the list
;#
;# Preconditions:
;# none
;#
;# Postconditions:
;# none
;#
;
.asg "", C62_set$regs
C62_set .macro ab_mask, c_mask, reglist
.var abmask,cmask,reg
.asg 0,abmask
.asg 0,cmask
.loop ; loop thru all regs in list
.break $ismember(reg,reglist) == 0 ; break when no more in list
.if $symcmp(reg,"a0") == 0 ; A registers
.eval abmask | C62_A0, abmask
.elseif $symcmp(reg,"A0") == 0
.eval abmask | C62_A0, abmask
.elseif $symcmp(reg,"a1") == 0
.eval abmask | C62_A1, abmask
.elseif $symcmp(reg,"A1") == 0
.eval abmask | C62_A1, abmask
.elseif $symcmp(reg,"a2") == 0
.eval abmask | C62_A2, abmask
.elseif $symcmp(reg,"A2") == 0
.eval abmask | C62_A2, abmask
.elseif $symcmp(reg,"a3") == 0
.eval abmask | C62_A3, abmask
.elseif $symcmp(reg,"A3") == 0
.eval abmask | C62_A3, abmask
.elseif $symcmp(reg,"a4") == 0
.eval abmask | C62_A4, abmask
.elseif $symcmp(reg,"A4") == 0
.eval abmask | C62_A4, abmask
.elseif $symcmp(reg,"a5") == 0
.eval abmask | C62_A5, abmask
.elseif $symcmp(reg,"A5") == 0
.eval abmask | C62_A5, abmask
.elseif $symcmp(reg,"a6") == 0
.eval abmask | C62_A6, abmask
.elseif $symcmp(reg,"A6") == 0
.eval abmask | C62_A6, abmask
.elseif $symcmp(reg,"a7") == 0
.eval abmask | C62_A7, abmask
.elseif $symcmp(reg,"A7") == 0
.eval abmask | C62_A7, abmask
.elseif $symcmp(reg,"a8") == 0
.eval abmask | C62_A8, abmask
.elseif $symcmp(reg,"A8") == 0
.eval abmask | C62_A8, abmask
.elseif $symcmp(reg,"a9") == 0
.eval abmask | C62_A9, abmask
.elseif $symcmp(reg,"A9") == 0
.eval abmask | C62_A9, abmask
.elseif $symcmp(reg,"a10") == 0
.eval abmask | C62_A10, abmask
.elseif $symcmp(reg,"A10") == 0
.eval abmask | C62_A10, abmask
.elseif $symcmp(reg,"a11") == 0
.eval abmask | C62_A11, abmask
.elseif $symcmp(reg,"A11") == 0
.eval abmask | C62_A11, abmask
.elseif $symcmp(reg,"a12") == 0
.eval abmask | C62_A12, abmask
.elseif $symcmp(reg,"A12") == 0
.eval abmask | C62_A12, abmask
.elseif $symcmp(reg,"a13") == 0
.eval abmask | C62_A13, abmask
.elseif $symcmp(reg,"A13") == 0
.eval abmask | C62_A13, abmask
.elseif $symcmp(reg,"a14") == 0
.eval abmask | C62_A14, abmask
.elseif $symcmp(reg,"A14") == 0
.eval abmask | C62_A14, abmask
.elseif $symcmp(reg,"a15") == 0
.eval abmask | C62_A15, abmask
.elseif $symcmp(reg,"A15") == 0
.eval abmask | C62_A15, abmask
.elseif $symcmp(reg,"b0") == 0 ; B registers
.eval abmask | C62_B0, abmask
.elseif $symcmp(reg,"B0") == 0
.eval abmask | C62_B0, abmask
.elseif $symcmp(reg,"b1") == 0
.eval abmask | C62_B1, abmask
.elseif $symcmp(reg,"B1") == 0
.eval abmask | C62_B1, abmask
.elseif $symcmp(reg,"b2") == 0
.eval abmask | C62_B2, abmask
.elseif $symcmp(reg,"B2") == 0
.eval abmask | C62_B2, abmask
.elseif $symcmp(reg,"b3") == 0
.eval abmask | C62_B3, abmask
.elseif $symcmp(reg,"B3") == 0
.eval abmask | C62_B3, abmask
.elseif $symcmp(reg,"b4") == 0
.eval abmask | C62_B4, abmask
.elseif $symcmp(reg,"B4") == 0
.eval abmask | C62_B4, abmask
.elseif $symcmp(reg,"b5") == 0
.eval abmask | C62_B5, abmask
.elseif $symcmp(reg,"B5") == 0
.eval abmask | C62_B5, abmask
.elseif $symcmp(reg,"b6") == 0
.eval abmask | C62_B6, abmask
.elseif $symcmp(reg,"B6") == 0
.eval abmask | C62_B6, abmask
.elseif $symcmp(reg,"b7") == 0
.eval abmask | C62_B7, abmask
.elseif $symcmp(reg,"B7") == 0
.eval abmask | C62_B7, abmask
.elseif $symcmp(reg,"b8") == 0
.eval abmask | C62_B8, abmask
.elseif $symcmp(reg,"B8") == 0
.eval abmask | C62_B8, abmask
.elseif $symcmp(reg,"b9") == 0
.eval abmask | C62_B9, abmask
.elseif $symcmp(reg,"B9") == 0
.eval abmask | C62_B9, abmask
.elseif $symcmp(reg,"b10") == 0
.eval abmask | C62_B10, abmask
.elseif $symcmp(reg,"B10") == 0
.eval abmask | C62_B10, abmask
.elseif $symcmp(reg,"b11") == 0
.eval abmask | C62_B11, abmask
.elseif $symcmp(reg,"B11") == 0
.eval abmask | C62_B11, abmask
.elseif $symcmp(reg,"b12") == 0
.eval abmask | C62_B12, abmask
.elseif $symcmp(reg,"B12") == 0
.eval abmask | C62_B12, abmask
.elseif $symcmp(reg,"b13") == 0
.eval abmask | C62_B13, abmask
.elseif $symcmp(reg,"B13") == 0
.eval abmask | C62_B13, abmask
.elseif $symcmp(reg,"b14") == 0
.eval abmask | C62_B14, abmask
.elseif $symcmp(reg,"B14") == 0
.eval abmask | C62_B14, abmask
.elseif $symcmp(reg,"b15") == 0
.eval abmask | C62_B15, abmask
.elseif $symcmp(reg,"B15") == 0
.eval abmask | C62_B15, abmask
.elseif $symcmp(reg,"amr") == 0 ; control registers
.eval cmask | C62_AMR, cmask
.elseif $symcmp(reg,"AMR") == 0
.eval cmask | C62_AMR, cmask
.elseif $symcmp(reg,"csr") == 0
.eval cmask | C62_CSR, cmask
.elseif $symcmp(reg,"CSR") == 0
.eval cmask | C62_CSR, cmask
.elseif $symcmp(reg,"ier") == 0
.eval cmask | C62_IER, cmask
.elseif $symcmp(reg,"IER") == 0
.eval cmask | C62_IER, cmask
.elseif $symcmp(reg,"ist") == 0
.eval cmask | C62_IST, cmask
.elseif $symcmp(reg,"IST") == 0
.eval cmask | C62_IST, cmask
.elseif $symcmp(reg,"irp") == 0
.eval cmask | C62_IRP, cmask
.elseif $symcmp(reg,"IRP") == 0
.eval cmask | C62_IRP, cmask
.elseif $symcmp(reg,"nrp") == 0
.eval cmask | C62_NRP, cmask
.elseif $symcmp(reg,"NRP") == 0
.eval cmask | C62_NRP, cmask
.else
.emsg "Bad register name in C62_set - :reg:"
.endif
.endloop
ab_mask .set abmask
c_mask .set cmask
.endm
;
;# ======== C62_disableIER ========
;
; Disable interrupts using mask
; IEMASK - Interrupt Enable mask
; REG0, REG1 - temporary registers used to set IER
;
;#
;# Preconditions:
;# none
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