csl_dmahal.h

SEED的VPM642测试程序-板级支持库

  #define _DMA_SECCTL_BLOCKIE_MASK      0x00000080u
  #define _DMA_SECCTL_BLOCKIE_SHIFT     0x00000007u
  #define  DMA_SECCTL_BLOCKIE_DEFAULT   0x00000001u
  #define  DMA_SECCTL_BLOCKIE_OF(x)     _VALUEOF(x)
  #define  DMA_SECCTL_BLOCKIE_DISABLE   0x00000000u
  #define  DMA_SECCTL_BLOCKIE_ENABLE    0x00000001u

  #define _DMA_SECCTL_BLOCKCOND_MASK    0x00000040u
  #define _DMA_SECCTL_BLOCKCOND_SHIFT   0x00000006u
  #define  DMA_SECCTL_BLOCKCOND_DEFAULT 0x00000000u
  #define  DMA_SECCTL_BLOCKCOND_OF(x)   _VALUEOF(x)
  #define  DMA_SECCTL_BLOCKCOND_CLEAR   0x00000000u
  #define  DMA_SECCTL_BLOCKCOND_SET     0x00000001u

  #define _DMA_SECCTL_LASTIE_MASK       0x00000020u
  #define _DMA_SECCTL_LASTIE_SHIFT      0x00000005u
  #define  DMA_SECCTL_LASTIE_DEFAULT    0x00000000u
  #define  DMA_SECCTL_LASTIE_OF(x)      _VALUEOF(x)
  #define  DMA_SECCTL_LASTIE_DISABLE    0x00000000u
  #define  DMA_SECCTL_LASTIE_ENABLE     0x00000001u

  #define _DMA_SECCTL_LASTCOND_MASK     0x00000010u
  #define _DMA_SECCTL_LASTCOND_SHIFT    0x00000004u
  #define  DMA_SECCTL_LASTCOND_DEFAULT  0x00000000u
  #define  DMA_SECCTL_LASTCOND_OF(x)    _VALUEOF(x)
  #define  DMA_SECCTL_LASTCOND_CLEAR    0x00000000u
  #define  DMA_SECCTL_LASTCOND_SET      0x00000001u

  #define _DMA_SECCTL_FRAMEIE_MASK      0x00000008u
  #define _DMA_SECCTL_FRAMEIE_SHIFT     0x00000003u
  #define  DMA_SECCTL_FRAMEIE_DEFAULT   0x00000000u
  #define  DMA_SECCTL_FRAMEIE_OF(x)     _VALUEOF(x)
  #define  DMA_SECCTL_FRAMEIE_DISABLE   0x00000000u
  #define  DMA_SECCTL_FRAMEIE_ENABLE    0x00000001u

  #define _DMA_SECCTL_FRAMECOND_MASK    0x00000004u
  #define _DMA_SECCTL_FRAMECOND_SHIFT   0x00000002u
  #define  DMA_SECCTL_FRAMECOND_DEFAULT 0x00000000u
  #define  DMA_SECCTL_FRAMECOND_OF(x)   _VALUEOF(x)
  #define  DMA_SECCTL_FRAMECOND_CLEAR   0x00000000u
  #define  DMA_SECCTL_FRAMECOND_SET     0x00000001u

  #define _DMA_SECCTL_SXIE_MASK         0x00000002u
  #define _DMA_SECCTL_SXIE_SHIFT        0x00000001u
  #define  DMA_SECCTL_SXIE_DEFAULT      0x00000000u
  #define  DMA_SECCTL_SXIE_OF(x)        _VALUEOF(x)
  #define  DMA_SECCTL_SXIE_DISABLE      0x00000000u
  #define  DMA_SECCTL_SXIE_ENABLE       0x00000001u

  #define _DMA_SECCTL_SXCOND_MASK       0x00000001u
  #define _DMA_SECCTL_SXCOND_SHIFT      0x00000000u
  #define  DMA_SECCTL_SXCOND_DEFAULT    0x00000000u
  #define  DMA_SECCTL_SXCOND_OF(x)      _VALUEOF(x)
  #define  DMA_SECCTL_SXCOND_CLEAR      0x00000000u
  #define  DMA_SECCTL_SXCOND_SET        0x00000001u

  #define  DMA_SECCTL_OF(x)             _VALUEOF(x)

#if (_DMA_COND1)
  #define DMA_SECCTL_DEFAULT (Uint32)( \
     _PER_FDEFAULT(DMA,SECCTL,WSPOL)\
    |_PER_FDEFAULT(DMA,SECCTL,RSPOL)\
    |_PER_FDEFAULT(DMA,SECCTL,FSIG)\
    |_PER_FDEFAULT(DMA,SECCTL,DMACEN)\
    |_PER_FDEFAULT(DMA,SECCTL,WSYNCCLR)\
    |_PER_FDEFAULT(DMA,SECCTL,WSYNCSTAT)\
    |_PER_FDEFAULT(DMA,SECCTL,RSYNCCLR)\
    |_PER_FDEFAULT(DMA,SECCTL,RSYNCSTAT)\
    |_PER_FDEFAULT(DMA,SECCTL,WDROPIE)\
    |_PER_FDEFAULT(DMA,SECCTL,WDROPCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,RDROPIE)\
    |_PER_FDEFAULT(DMA,SECCTL,RDROPCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,BLOCKIE)\
    |_PER_FDEFAULT(DMA,SECCTL,BLOCKCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,LASTIE)\
    |_PER_FDEFAULT(DMA,SECCTL,LASTCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,FRAMEIE)\
    |_PER_FDEFAULT(DMA,SECCTL,FRAMECOND)\
    |_PER_FDEFAULT(DMA,SECCTL,SXIE)\
    |_PER_FDEFAULT(DMA,SECCTL,SXCOND)\
  )

  #define DMA_SECCTL_RMK(wspol,rspol,fsig,dmacen,wsyncclr,wsyncstat,rsyncclr,\
    rsyncstat,wdropie,wdropcond,rdropie,rdropcond,blockie,blockcond,\
    lastie,lastcond,frameie,framecond,sxie,sxcond) (Uint32)( \
     _PER_FMK(DMA,SECCTL,WSPOL,wspol)\
    |_PER_FMK(DMA,SECCTL,RSPOL,rspol)\
    |_PER_FMK(DMA,SECCTL,FSIG,fsig)\
    |_PER_FMK(DMA,SECCTL,DMACEN,dmacen)\
    |_PER_FMK(DMA,SECCTL,WSYNCCLR,wsyncclr)\
    |_PER_FMK(DMA,SECCTL,WSYNCSTAT,wsyncstat)\
    |_PER_FMK(DMA,SECCTL,RSYNCCLR,rsyncclr)\
    |_PER_FMK(DMA,SECCTL,RSYNCSTAT,rsyncstat)\
    |_PER_FMK(DMA,SECCTL,WDROPIE,wdropie)\
    |_PER_FMK(DMA,SECCTL,WDROPCOND,wdropcond)\
    |_PER_FMK(DMA,SECCTL,RDROPIE,rdropie)\
    |_PER_FMK(DMA,SECCTL,RDROPCOND,rdropcond)\
    |_PER_FMK(DMA,SECCTL,BLOCKIE,blockie)\
    |_PER_FMK(DMA,SECCTL,BLOCKCOND,blockcond)\
    |_PER_FMK(DMA,SECCTL,LASTIE,lastie)\
    |_PER_FMK(DMA,SECCTL,LASTCOND,lastcond)\
    |_PER_FMK(DMA,SECCTL,FRAMEIE,frameie)\
    |_PER_FMK(DMA,SECCTL,FRAMECOND,framecond)\
    |_PER_FMK(DMA,SECCTL,SXIE,sxie)\
    |_PER_FMK(DMA,SECCTL,SXCOND,sxcond)\
  )
#endif

#if (!_DMA_COND1)
  #define DMA_SECCTL_DEFAULT (Uint32)( \
     _PER_FDEFAULT(DMA,SECCTL,DMACEN)\
    |_PER_FDEFAULT(DMA,SECCTL,WSYNCCLR)\
    |_PER_FDEFAULT(DMA,SECCTL,WSYNCSTAT)\
    |_PER_FDEFAULT(DMA,SECCTL,RSYNCCLR)\
    |_PER_FDEFAULT(DMA,SECCTL,RSYNCSTAT)\
    |_PER_FDEFAULT(DMA,SECCTL,WDROPIE)\
    |_PER_FDEFAULT(DMA,SECCTL,WDROPCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,RDROPIE)\
    |_PER_FDEFAULT(DMA,SECCTL,RDROPCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,BLOCKIE)\
    |_PER_FDEFAULT(DMA,SECCTL,BLOCKCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,LASTIE)\
    |_PER_FDEFAULT(DMA,SECCTL,LASTCOND)\
    |_PER_FDEFAULT(DMA,SECCTL,FRAMEIE)\
    |_PER_FDEFAULT(DMA,SECCTL,FRAMECOND)\
    |_PER_FDEFAULT(DMA,SECCTL,SXIE)\
    |_PER_FDEFAULT(DMA,SECCTL,SXCOND)\
  )

  #define DMA_SECCTL_RMK(dmacen,wsyncclr,wsyncstat,rsyncclr,\
    rsyncstat,wdropie,wdropcond,rdropie,rdropcond,blockie,blockcond,\
    lastie,lastcond,frameie,framecond,sxie,sxcond) (Uint32)( \
     _PER_FMK(DMA,SECCTL,DMACEN,dmacen)\
    |_PER_FMK(DMA,SECCTL,WSYNCCLR,wsyncclr)\
    |_PER_FMK(DMA,SECCTL,WSYNCSTAT,wsyncstat)\
    |_PER_FMK(DMA,SECCTL,RSYNCCLR,rsyncclr)\
    |_PER_FMK(DMA,SECCTL,RSYNCSTAT,rsyncstat)\
    |_PER_FMK(DMA,SECCTL,WDROPIE,wdropie)\
    |_PER_FMK(DMA,SECCTL,WDROPCOND,wdropcond)\
    |_PER_FMK(DMA,SECCTL,RDROPIE,rdropie)\
    |_PER_FMK(DMA,SECCTL,RDROPCOND,rdropcond)\
    |_PER_FMK(DMA,SECCTL,BLOCKIE,blockie)\
    |_PER_FMK(DMA,SECCTL,BLOCKCOND,blockcond)\
    |_PER_FMK(DMA,SECCTL,LASTIE,lastie)\
    |_PER_FMK(DMA,SECCTL,LASTCOND,lastcond)\
    |_PER_FMK(DMA,SECCTL,FRAMEIE,frameie)\
    |_PER_FMK(DMA,SECCTL,FRAMECOND,framecond)\
    |_PER_FMK(DMA,SECCTL,SXIE,sxie)\
    |_PER_FMK(DMA,SECCTL,SXCOND,sxcond)\
  )
#endif

  #define _DMA_SECCTL_COND_MASK (\
     _DMA_SECCTL_WDROPCOND_MASK\
    |_DMA_SECCTL_RDROPCOND_MASK\
    |_DMA_SECCTL_BLOCKCOND_MASK\
    |_DMA_SECCTL_LASTCOND_MASK\
    |_DMA_SECCTL_FRAMECOND_MASK\
    |_DMA_SECCTL_SXCOND_MASK\
  )

  #define _DMA_SECCTL_IE_MASK (\
     _DMA_SECCTL_WDROPIE_MASK\
    |_DMA_SECCTL_RDROPIE_MASK\
    |_DMA_SECCTL_BLOCKIE_MASK\
    |_DMA_SECCTL_LASTIE_MASK\
    |_DMA_SECCTL_FRAMEIE_MASK\
    |_DMA_SECCTL_SXIE_MASK\
  )

  #define _DMA_SECCTL_STAT_MASK (\
     _DMA_SECCTL_WSYNCSTAT_MASK\
    |_DMA_SECCTL_RSYNCSTAT_MASK\
  )

  #define _DMA_SECCTL_CLR_MASK (\
     _DMA_SECCTL_WSYNCCLR_MASK\
    |_DMA_SECCTL_RSYNCCLR_MASK\
  )

  #define _DMA_SECCTL_FGET(N,FIELD)\
    _PER_FGET(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,##FIELD)

  #define _DMA_SECCTL_FSET(N,FIELD,field)\
    _PER_RAOI(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,\
      (0xFFFF0AAA&~_DMA_SECCTL_##FIELD##_MASK),\
      (0x00000555&~_DMA_SECCTL_##FIELD##_MASK)\
      |_PER_FMK(DMA,SECCTL,##FIELD,field),\
      0x00000000\
    )

  #define _DMA_SECCTL_FSETS(N,FIELD,SYM)\
    _PER_RAOI(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,\
      (0xFFFF0AAA&~_DMA_SECCTL_##FIELD##_MASK),\
      (0x00000555&~_DMA_SECCTL_##FIELD##_MASK)\
      |_PER_FMKS(DMA,SECCTL,##FIELD,##SYM),\
      0x00000000\
    )

  #define _DMA_SECCTL0_FGET(FIELD) _DMA_SECCTL_FGET(0,##FIELD)
  #define _DMA_SECCTL1_FGET(FIELD) _DMA_SECCTL_FGET(1,##FIELD)
  #define _DMA_SECCTL2_FGET(FIELD) _DMA_SECCTL_FGET(2,##FIELD)
  #define _DMA_SECCTL3_FGET(FIELD) _DMA_SECCTL_FGET(3,##FIELD)

  #define _DMA_SECCTL0_FSET(FIELD,f) _DMA_SECCTL_FSET(0,##FIELD,f)
  #define _DMA_SECCTL1_FSET(FIELD,f) _DMA_SECCTL_FSET(1,##FIELD,f)
  #define _DMA_SECCTL2_FSET(FIELD,f) _DMA_SECCTL_FSET(2,##FIELD,f)
  #define _DMA_SECCTL3_FSET(FIELD,f) _DMA_SECCTL_FSET(3,##FIELD,f)

  #define _DMA_SECCTL0_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(0,##FIELD,##SYM)
  #define _DMA_SECCTL1_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(1,##FIELD,##SYM)
  #define _DMA_SECCTL2_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(2,##FIELD,##SYM)
  #define _DMA_SECCTL3_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(3,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  S R C            |
* |___________________|
*
* SRC0     - channel src address register 0
* SRC1     - channel src address register 1
* SRC2     - channel src address register 2
* SRC3     - channel src address register 3
*
* FIELDS (msb -> lsb)
* (rw) SRC
*
\******************************************************************************/
  #define _DMA_SRC_OFFSET               4

  #define _DMA_SRC0_ADDR                0x01840010u
  #define _DMA_SRC1_ADDR                0x01840050u
  #define _DMA_SRC2_ADDR                0x01840014u
  #define _DMA_SRC3_ADDR                0x01840054u

  #define _DMA_SRC_SRC_MASK             0xFFFFFFFFu
  #define _DMA_SRC_SRC_SHIFT            0x00000000u
  #define  DMA_SRC_SRC_DEFAULT          0x00000000u
  #define  DMA_SRC_SRC_OF(x)            _VALUEOF(x)

  #define  DMA_SRC_OF(x)                _VALUEOF(x)

  #define DMA_SRC_DEFAULT (Uint32)( \
     _PER_FDEFAULT(DMA,SRC,SRC) \
  )

  #define DMA_SRC_RMK(src) (Uint32)( \
     _PER_FMK(DMA,SRC,SRC,src) \
  )

  #define _DMA_SRC_FGET(N,FIELD)\
    _PER_FGET(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD)

  #define _DMA_SRC_FSET(N,FIELD,field)\
    _PER_FSET(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD,field)

  #define _DMA_SRC_FSETS(N,FIELD,SYM)\
    _PER_FSETS(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD,##SYM)

  #define _DMA_SRC0_FGET(FIELD) _DMA_SRC_FGET(0,##FIELD)
  #define _DMA_SRC1_FGET(FIELD) _DMA_SRC_FGET(1,##FIELD)
  #define _DMA_SRC2_FGET(FIELD) _DMA_SRC_FGET(2,##FIELD)
  #define _DMA_SRC3_FGET(FIELD) _DMA_SRC_FGET(3,##FIELD)

  #define _DMA_SRC0_FSET(FIELD,f) _DMA_SRC_FSET(0,##FIELD,f)
  #define _DMA_SRC1_FSET(FIELD,f) _DMA_SRC_FSET(1,##FIELD,f)
  #define _DMA_SRC2_FSET(FIELD,f) _DMA_SRC_FSET(2,##FIELD,f)
  #define _DMA_SRC3_FSET(FIELD,f) _DMA_SRC_FSET(3,##FIELD,f)

  #define _DMA_SRC0_FSETS(FIELD,SYM) _DMA_SRC_FSETS(0,##FIELD,##SYM)
  #define _DMA_SRC1_FSETS(FIELD,SYM) _DMA_SRC_FSETS(1,##FIELD,##SYM)
  #define _DMA_SRC2_FSETS(FIELD,SYM) _DMA_SRC_FSETS(2,##FIELD,##SYM)
  #define _DMA_SRC3_FSETS(FIELD,SYM) _DMA_SRC_FSETS(3,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  D S T            |
* |___________________|
*
* DST0     - channel destination address register 0
* DST1     - channel destination address register 1
* DST2     - channel destination address register 2
* DST3     - channel destination address register 3
*
* * - handle based
*
* FIELDS (msb -> lsb)
* (rw) DST
*
\******************************************************************************/
  #define _DMA_DST_OFFSET               6

  #define _DMA_DST0_ADDR                0x01840018u
  #define _DMA_DST1_ADDR                0x01840058u
  #define _DMA_DST2_ADDR                0x0184001Cu