csl_dmahal.h

SEED的VPM642测试程序-板级支持库

  #define  DMA_PRICTL_WSYNC_REVT0       0x0000000Du
  #define  DMA_PRICTL_WSYNC_XEVT1       0x0000000Eu
  #define  DMA_PRICTL_WSYNC_REVT1       0x0000000Fu
  #define  DMA_PRICTL_WSYNC_DSPINT      0x00000010u
  #define  DMA_PRICTL_WSYNC_XEVT2       0x00000011u
  #define  DMA_PRICTL_WSYNC_REVT2       0x00000012u

  #define _DMA_PRICTL_RSYNC_MASK        0x0007C000u
  #define _DMA_PRICTL_RSYNC_SHIFT       0x0000000Eu
  #define  DMA_PRICTL_RSYNC_DEFAULT     0x00000000u
  #define  DMA_PRICTL_RSYNC_OF(x)       _VALUEOF(x)
  #define  DMA_PRICTL_RSYNC_NONE        0x00000000u
  #define  DMA_PRICTL_RSYNC_TINT0       0x00000001u
  #define  DMA_PRICTL_RSYNC_TINT1       0x00000002u
  #define  DMA_PRICTL_RSYNC_SDINT       0x00000003u
  #define  DMA_PRICTL_RSYNC_EXTINT4     0x00000004u
  #define  DMA_PRICTL_RSYNC_EXTINT5     0x00000005u
  #define  DMA_PRICTL_RSYNC_EXTINT6     0x00000006u
  #define  DMA_PRICTL_RSYNC_EXTINT7     0x00000007u
  #define  DMA_PRICTL_RSYNC_DMAINT0     0x00000008u
  #define  DMA_PRICTL_RSYNC_DMAINT1     0x00000009u
  #define  DMA_PRICTL_RSYNC_DMAINT2     0x0000000Au
  #define  DMA_PRICTL_RSYNC_DMAINT3     0x0000000Bu
  #define  DMA_PRICTL_RSYNC_XEVT0       0x0000000Cu
  #define  DMA_PRICTL_RSYNC_REVT0       0x0000000Du
  #define  DMA_PRICTL_RSYNC_XEVT1       0x0000000Eu
  #define  DMA_PRICTL_RSYNC_REVT1       0x0000000Fu
  #define  DMA_PRICTL_RSYNC_DSPINT      0x00000010u
  #define  DMA_PRICTL_RSYNC_XEVT2       0x00000011u
  #define  DMA_PRICTL_RSYNC_REVT2       0x00000012u

  #define _DMA_PRICTL_INDEX_MASK        0x00002000u
  #define _DMA_PRICTL_INDEX_SHIFT       0x0000000Du
  #define  DMA_PRICTL_INDEX_DEFAULT     0x00000000u
  #define  DMA_PRICTL_INDEX_OF(x)       _VALUEOF(x)
  #define  DMA_PRICTL_INDEX_NA          0x00000000u
  #define  DMA_PRICTL_INDEX_A           0x00000000u
  #define  DMA_PRICTL_INDEX_B           0x00000001u

  #define _DMA_PRICTL_CNTRLD_MASK       0x00001000u
  #define _DMA_PRICTL_CNTRLD_SHIFT      0x0000000Cu
  #define  DMA_PRICTL_CNTRLD_DEFAULT    0x00000000u
  #define  DMA_PRICTL_CNTRLD_OF(x)      _VALUEOF(x)
  #define  DMA_PRICTL_CNTRLD_NA         0x00000000u
  #define  DMA_PRICTL_CNTRLD_A          0x00000000u
  #define  DMA_PRICTL_CNTRLD_B          0x00000001u

  #define _DMA_PRICTL_SPLIT_MASK        0x00000C00u
  #define _DMA_PRICTL_SPLIT_SHIFT       0x0000000Au
  #define  DMA_PRICTL_SPLIT_DEFAULT     0x00000000u
  #define  DMA_PRICTL_SPLIT_OF(x)       _VALUEOF(x)
  #define  DMA_PRICTL_SPLIT_DISABLE     0x00000000u
  #define  DMA_PRICTL_SPLIT_A           0x00000001u
  #define  DMA_PRICTL_SPLIT_B           0x00000002u
  #define  DMA_PRICTL_SPLIT_C           0x00000003u

  #define _DMA_PRICTL_ESIZE_MASK        0x00000300u
  #define _DMA_PRICTL_ESIZE_SHIFT       0x00000008u
  #define  DMA_PRICTL_ESIZE_DEFAULT     0x00000000u
  #define  DMA_PRICTL_ESIZE_OF(x)       _VALUEOF(x)
  #define  DMA_PRICTL_ESIZE_32BIT       0x00000000u
  #define  DMA_PRICTL_ESIZE_16BIT       0x00000001u
  #define  DMA_PRICTL_ESIZE_8BIT        0x00000002u

  #define _DMA_PRICTL_DSTDIR_MASK       0x000000C0u
  #define _DMA_PRICTL_DSTDIR_SHIFT      0x00000006u
  #define  DMA_PRICTL_DSTDIR_DEFAULT    0x00000000u
  #define  DMA_PRICTL_DSTDIR_OF(x)      _VALUEOF(x)
  #define  DMA_PRICTL_DSTDIR_NONE       0x00000000u
  #define  DMA_PRICTL_DSTDIR_INC        0x00000001u
  #define  DMA_PRICTL_DSTDIR_DEC        0x00000002u
  #define  DMA_PRICTL_DSTDIR_IDX        0x00000003u

  #define _DMA_PRICTL_SRCDIR_MASK       0x00000030u
  #define _DMA_PRICTL_SRCDIR_SHIFT      0x00000004u
  #define  DMA_PRICTL_SRCDIR_DEFAULT    0x00000000u
  #define  DMA_PRICTL_SRCDIR_OF(x)      _VALUEOF(x)
  #define  DMA_PRICTL_SRCDIR_NONE       0x00000000u
  #define  DMA_PRICTL_SRCDIR_INC        0x00000001u
  #define  DMA_PRICTL_SRCDIR_DEC        0x00000002u
  #define  DMA_PRICTL_SRCDIR_IDX        0x00000003u

  #define _DMA_PRICTL_STATUS_MASK       0x0000000Cu
  #define _DMA_PRICTL_STATUS_SHIFT      0x00000002u
  #define  DMA_PRICTL_STATUS_DEFAULT    0x00000000u
  #define  DMA_PRICTL_STATUS_OF(x)      _VALUEOF(x)
  #define  DMA_PRICTL_STATUS_STOPPED    0x00000000u
  #define  DMA_PRICTL_STATUS_RUNNING    0x00000001u
  #define  DMA_PRICTL_STATUS_PAUSED     0x00000002u
  #define  DMA_PRICTL_STATUS_AUTORUNNING 0x00000003u

  #define _DMA_PRICTL_START_MASK        0x00000003u
  #define _DMA_PRICTL_START_SHIFT       0x00000000u
  #define  DMA_PRICTL_START_DEFAULT     0x00000000u
  #define  DMA_PRICTL_START_OF(x)       _VALUEOF(x)
  #define  DMA_PRICTL_START_STOP        0x00000000u
  #define  DMA_PRICTL_START_NORMAL      0x00000001u
  #define  DMA_PRICTL_START_PAUSE       0x00000002u
  #define  DMA_PRICTL_START_AUTOINIT    0x00000003u

  #define  DMA_PRICTL_OF(x)             _VALUEOF(x)

  #define DMA_PRICTL_DEFAULT (Uint32)( \
     _PER_FDEFAULT(DMA,PRICTL,DSTRLD)\
    |_PER_FDEFAULT(DMA,PRICTL,SRCRLD)\
    |_PER_FDEFAULT(DMA,PRICTL,EMOD)\
    |_PER_FDEFAULT(DMA,PRICTL,FS)\
    |_PER_FDEFAULT(DMA,PRICTL,TCINT)\
    |_PER_FDEFAULT(DMA,PRICTL,PRI)\
    |_PER_FDEFAULT(DMA,PRICTL,WSYNC)\
    |_PER_FDEFAULT(DMA,PRICTL,RSYNC)\
    |_PER_FDEFAULT(DMA,PRICTL,INDEX)\
    |_PER_FDEFAULT(DMA,PRICTL,CNTRLD)\
    |_PER_FDEFAULT(DMA,PRICTL,SPLIT)\
    |_PER_FDEFAULT(DMA,PRICTL,ESIZE)\
    |_PER_FDEFAULT(DMA,PRICTL,DSTDIR)\
    |_PER_FDEFAULT(DMA,PRICTL,SRCDIR)\
    |_PER_FDEFAULT(DMA,PRICTL,STATUS)\
    |_PER_FDEFAULT(DMA,PRICTL,START)\
  )

  #define DMA_PRICTL_RMK(dstrld,srcrld,emod,fs,tcint,pri,wsync,rsync,index,\
    cntrld,split,esize,dstdir,srcdir,start) (Uint32)( \
     _PER_FMK(DMA,PRICTL,DSTRLD,dstrld)\
    |_PER_FMK(DMA,PRICTL,SRCRLD,srcrld)\
    |_PER_FMK(DMA,PRICTL,EMOD,emod)\
    |_PER_FMK(DMA,PRICTL,FS,fs)\
    |_PER_FMK(DMA,PRICTL,TCINT,tcint)\
    |_PER_FMK(DMA,PRICTL,PRI,pri)\
    |_PER_FMK(DMA,PRICTL,WSYNC,wsync)\
    |_PER_FMK(DMA,PRICTL,RSYNC,rsync)\
    |_PER_FMK(DMA,PRICTL,INDEX,index)\
    |_PER_FMK(DMA,PRICTL,CNTRLD,cntrld)\
    |_PER_FMK(DMA,PRICTL,SPLIT,split)\
    |_PER_FMK(DMA,PRICTL,ESIZE,esize)\
    |_PER_FMK(DMA,PRICTL,DSTDIR,dstdir)\
    |_PER_FMK(DMA,PRICTL,SRCDIR,srcdir)\
    |_PER_FMK(DMA,PRICTL,START,start)\
  )

  #define _DMA_PRICTL_FGET(N,FIELD)\
    _PER_FGET(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD)

  #define _DMA_PRICTL_FSET(N,FIELD,field)\
    _PER_FSET(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD,field)

  #define _DMA_PRICTL_FSETS(N,FIELD,SYM)\
    _PER_FSETS(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD,##SYM)

  #define _DMA_PRICTL0_FGET(FIELD) _DMA_PRICTL_FGET(0,##FIELD)
  #define _DMA_PRICTL1_FGET(FIELD) _DMA_PRICTL_FGET(1,##FIELD)
  #define _DMA_PRICTL2_FGET(FIELD) _DMA_PRICTL_FGET(2,##FIELD)
  #define _DMA_PRICTL3_FGET(FIELD) _DMA_PRICTL_FGET(3,##FIELD)

  #define _DMA_PRICTL0_FSET(FIELD,f) _DMA_PRICTL_FSET(0,##FIELD,f)
  #define _DMA_PRICTL1_FSET(FIELD,f) _DMA_PRICTL_FSET(1,##FIELD,f)
  #define _DMA_PRICTL2_FSET(FIELD,f) _DMA_PRICTL_FSET(2,##FIELD,f)
  #define _DMA_PRICTL3_FSET(FIELD,f) _DMA_PRICTL_FSET(3,##FIELD,f)

  #define _DMA_PRICTL0_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(0,##FIELD,##SYM)
  #define _DMA_PRICTL1_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(1,##FIELD,##SYM)
  #define _DMA_PRICTL2_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(2,##FIELD,##SYM)
  #define _DMA_PRICTL3_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(3,##FIELD,##SYM)


/******************************************************************************\
* _____________________
* |                   |
* |  S E C C T L      |
* |___________________|
*
* SECCTL0  - channel seccondary control register 0
* SECCTL1  - channel seccondary control register 1
* SECCTL2  - channel seccondary control register 2
* SECCTL3  - channel seccondary control register 3
*
* FIELDS (msb -> lsb)
* (rw) WSPOL (1)
* (rw) RSPOL (1)
* (rw) FSIG  (1)
* (rw) DMACEN
* (rw) WSYNCCLR
* (rw) WSYNCSTAT
* (rw) RSYNCCLR
* (rw) RSYNCSTAT
* (rw) WDROPIE
* (rw) WDROPCOND
* (rw) RDROPIE
* (rw) RDROPCOND
* (rw) BLOCKIE
* (rw) BLOCKCOND
* (rw) LASTIE
* (rw) LASTCOND
* (rw) FRAMEIE
* (rw) FRAMECOND
* (rw) SXIE
* (rw) SXCOND
*
* (1) only on 6202 / 6203 /6204 /6205 devices
*
\******************************************************************************/
  #define _DMA_SECCTL_OFFSET            2

  #define _DMA_SECCTL0_ADDR             0x01840008u
  #define _DMA_SECCTL1_ADDR             0x01840048u
  #define _DMA_SECCTL2_ADDR             0x0184000Cu
  #define _DMA_SECCTL3_ADDR             0x0184004Cu

#if (_DMA_COND1)
  #define _DMA_SECCTL_WSPOL_MASK        0x00200000u
  #define _DMA_SECCTL_WSPOL_SHIFT       0x00000015u
  #define  DMA_SECCTL_WSPOL_DEFAULT     0x00000000u
  #define  DMA_SECCTL_WSPOL_OF(x)       _VALUEOF(x)
  #define  DMA_SECCTL_WSPOL_NA          0x00000000u
  #define  DMA_SECCTL_WSPOL_ACTIVEHIGH  0x00000000u
  #define  DMA_SECCTL_WSPOL_ACTIVELOW   0x00000001u

  #define _DMA_SECCTL_RSPOL_MASK        0x00100000u
  #define _DMA_SECCTL_RSPOL_SHIFT       0x00000014u
  #define  DMA_SECCTL_RSPOL_DEFAULT     0x00000000u
  #define  DMA_SECCTL_RSPOL_OF(x)       _VALUEOF(x)
  #define  DMA_SECCTL_RSPOL_NA          0x00000000u
  #define  DMA_SECCTL_RSPOL_ACTIVEHIGH  0x00000000u
  #define  DMA_SECCTL_RSPOL_ACTIVELOW   0x00000001u

  #define _DMA_SECCTL_FSIG_MASK         0x00080000u
  #define _DMA_SECCTL_FSIG_SHIFT        0x00000013u
  #define  DMA_SECCTL_FSIG_DEFAULT      0x00000000u
  #define  DMA_SECCTL_FSIG_OF(x)        _VALUEOF(x)
  #define  DMA_SECCTL_FSIG_NA           0x00000000u
  #define  DMA_SECCTL_FSIG_NORMAL       0x00000000u
  #define  DMA_SECCTL_FSIG_IGNORE       0x00000001u
#endif

  #define _DMA_SECCTL_DMACEN_MASK       0x00070000u
  #define _DMA_SECCTL_DMACEN_SHIFT      0x00000010u
  #define  DMA_SECCTL_DMACEN_DEFAULT    0x00000000u
  #define  DMA_SECCTL_DMACEN_OF(x)      _VALUEOF(x)
  #define  DMA_SECCTL_DMACEN_LOW        0x00000000u
  #define  DMA_SECCTL_DMACEN_HIGH       0x00000001u
  #define  DMA_SECCTL_DMACEN_RSYNCSTAT  0x00000002u
  #define  DMA_SECCTL_DMACEN_WSYNCSTAT  0x00000003u
  #define  DMA_SECCTL_DMACEN_FRAMECOND  0x00000004u
  #define  DMA_SECCTL_DMACEN_BLOCKCOND  0x00000005u

  #define _DMA_SECCTL_WSYNCCLR_MASK     0x00008000u
  #define _DMA_SECCTL_WSYNCCLR_SHIFT    0x0000000Fu
  #define  DMA_SECCTL_WSYNCCLR_DEFAULT  0x00000000u
  #define  DMA_SECCTL_WSYNCCLR_OF(x)    _VALUEOF(x)
  #define  DMA_SECCTL_WSYNCCLR_NOTHING  0x00000000u
  #define  DMA_SECCTL_WSYNCCLR_CLEAR    0x00000001u

  #define _DMA_SECCTL_WSYNCSTAT_MASK    0x00004000u
  #define _DMA_SECCTL_WSYNCSTAT_SHIFT   0x0000000Eu
  #define  DMA_SECCTL_WSYNCSTAT_DEFAULT 0x00000000u
  #define  DMA_SECCTL_WSYNCSTAT_OF(x)   _VALUEOF(x)
  #define  DMA_SECCTL_WSYNCSTAT_CLEAR   0x00000000u
  #define  DMA_SECCTL_WSYNCSTAT_SET     0x00000001u

  #define _DMA_SECCTL_RSYNCCLR_MASK     0x00002000u
  #define _DMA_SECCTL_RSYNCCLR_SHIFT    0x0000000Du
  #define  DMA_SECCTL_RSYNCCLR_DEFAULT  0x00000000u
  #define  DMA_SECCTL_RSYNCCLR_OF(x)    _VALUEOF(x)
  #define  DMA_SECCTL_RSYNCCLR_NOTHING  0x00000000u
  #define  DMA_SECCTL_RSYNCCLR_CLEAR    0x00000001u

  #define _DMA_SECCTL_RSYNCSTAT_MASK    0x00001000u
  #define _DMA_SECCTL_RSYNCSTAT_SHIFT   0x0000000Cu
  #define  DMA_SECCTL_RSYNCSTAT_DEFAULT 0x00000000u
  #define  DMA_SECCTL_RSYNCSTAT_OF(x)   _VALUEOF(x)
  #define  DMA_SECCTL_RSYNCSTAT_CLEAR   0x00000000u
  #define  DMA_SECCTL_RSYNCSTAT_SET     0x00000001u

  #define _DMA_SECCTL_WDROPIE_MASK      0x00000800u
  #define _DMA_SECCTL_WDROPIE_SHIFT     0x0000000Bu
  #define  DMA_SECCTL_WDROPIE_DEFAULT   0x00000000u
  #define  DMA_SECCTL_WDROPIE_OF(x)     _VALUEOF(x)
  #define  DMA_SECCTL_WDROPIE_DISABLE   0x00000000u
  #define  DMA_SECCTL_WDROPIE_ENABLE    0x00000001u

  #define _DMA_SECCTL_WDROPCOND_MASK    0x00000400u
  #define _DMA_SECCTL_WDROPCOND_SHIFT   0x0000000Au
  #define  DMA_SECCTL_WDROPCOND_DEFAULT 0x00000000u
  #define  DMA_SECCTL_WDROPCOND_OF(x)   _VALUEOF(x)
  #define  DMA_SECCTL_WDROPCOND_CLEAR   0x00000000u
  #define  DMA_SECCTL_WDROPCOND_SET     0x00000001u

  #define _DMA_SECCTL_RDROPIE_MASK      0x00000200u
  #define _DMA_SECCTL_RDROPIE_SHIFT     0x00000009u
  #define  DMA_SECCTL_RDROPIE_DEFAULT   0x00000000u
  #define  DMA_SECCTL_RDROPIE_OF(x)     _VALUEOF(x)
  #define  DMA_SECCTL_RDROPIE_DISABLE   0x00000000u
  #define  DMA_SECCTL_RDROPIE_ENABLE    0x00000001u

  #define _DMA_SECCTL_RDROPCOND_MASK    0x00000100u
  #define _DMA_SECCTL_RDROPCOND_SHIFT   0x00000008u
  #define  DMA_SECCTL_RDROPCOND_DEFAULT 0x00000000u
  #define  DMA_SECCTL_RDROPCOND_OF(x)   _VALUEOF(x)
  #define  DMA_SECCTL_RDROPCOND_CLEAR   0x00000000u
  #define  DMA_SECCTL_RDROPCOND_SET     0x00000001u