📄 csl_dmahal.h
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/******************************************************************************\
* Copyright (C) 1999-2000 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_dmahal.h
* DATE CREATED.. 03/12/1999
* LAST MODIFIED. 02/05/2002 added 6204/6205 to DMA_COND1
*------------------------------------------------------------------------------
* REGISTERS
*
* AUXCTL - auxiliary control register
* PRICTL0 - channel primary control register 0
* PRICTL1 - channel primary control register 1
* PRICTL2 - channel primary control register 2
* PRICTL3 - channel primary control register 3
* SECCTL0 - channel seccondary control register 0
* SECCTL1 - channel seccondary control register 1
* SECCTL2 - channel seccondary control register 2
* SECCTL3 - channel seccondary control register 3
* SRC0 - channel src address register 0
* SRC1 - channel src address register 1
* SRC2 - channel src address register 2
* SRC3 - channel src address register 3
* DST0 - channel destination address register 0
* DST1 - channel destination address register 1
* DST2 - channel destination address register 2
* DST3 - channel destination address register 3
* XFRCNT0 - channel transfer count register 0
* XFRCNT1 - channel transfer count register 1
* XFRCNT2 - channel transfer count register 2
* XFRCNT3 - channel transfer count register 3
* GBLCNTA - global count reload register A
* GBLCNTB - global count reload register B
* GBLIDXA - global index register A
* GBLIDXB - global index register B
* GBLADDRA - global address reload register A
* GBLADDRB - global address reload register B
* GBLADDRC - global address reload register C
* GBLADDRD - global address reload register D
*
\******************************************************************************/
#ifndef _CSL_DMAHAL_H_
#define _CSL_DMAHAL_H_
#include <csl_stdinc.h>
#include <csl_chip.h>
#if (DMA_SUPPORT)
/******************************************************************************\
* MISC section
\******************************************************************************/
#define _DMA_COND1 (CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205)
#define _DMA_BASE_CHA0 0x01840000u
#define _DMA_BASE_CHA1 0x01840040u
#define _DMA_BASE_CHA2 0x01840004u
#define _DMA_BASE_CHA3 0x01840044u
/******************************************************************************\
* module level register/field access macros
\******************************************************************************/
/* ----------------- */
/* FIELD MAKE MACROS */
/* ----------------- */
#define DMA_FMK(REG,FIELD,x)\
_PER_FMK(DMA,##REG,##FIELD,x)
#define DMA_FMKS(REG,FIELD,SYM)\
_PER_FMKS(DMA,##REG,##FIELD,##SYM)
/* -------------------------------- */
/* RAW REGISTER/FIELD ACCESS MACROS */
/* -------------------------------- */
#define DMA_ADDR(REG)\
_DMA_##REG##_ADDR
#define DMA_RGET(REG)\
_PER_RGET(_DMA_##REG##_ADDR,DMA,##REG)
#define DMA_RSET(REG,x)\
_PER_RSET(_DMA_##REG##_ADDR,DMA,##REG,x)
#define DMA_FGET(REG,FIELD)\
_DMA_##REG##_FGET(##FIELD)
#define DMA_FSET(REG,FIELD,x)\
_DMA_##REG##_FSET(##FIELD,##x)
#define DMA_FSETS(REG,FIELD,SYM)\
_DMA_##REG##_FSETS(##FIELD,##SYM)
/* ------------------------------------------ */
/* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */
/* ------------------------------------------ */
#define DMA_RGETA(addr,REG)\
_PER_RGET(addr,DMA,##REG)
#define DMA_RSETA(addr,REG,x)\
_PER_RSET(addr,DMA,##REG,x)
#define DMA_FGETA(addr,REG,FIELD)\
_PER_FGET(addr,DMA,##REG,##FIELD)
#define DMA_FSETA(addr,REG,FIELD,x)\
_PER_FSET(addr,DMA,##REG,##FIELD,x)
#define DMA_FSETSA(addr,REG,FIELD,SYM)\
_PER_FSETS(addr,DMA,##REG,##FIELD,##SYM)
/* ----------------------------------------- */
/* HANDLE BASED REGISTER/FIELD ACCESS MACROS */
/* ----------------------------------------- */
#define DMA_ADDRH(h,REG)\
(Uint32)(&((h)->baseAddr[_DMA_##REG##_OFFSET]))
#define DMA_RGETH(h,REG)\
DMA_RGETA(DMA_ADDRH(h,##REG),##REG)
#define DMA_RSETH(h,REG,x)\
DMA_RSETA(DMA_ADDRH(h,##REG),##REG,x)
#define DMA_FGETH(h,REG,FIELD)\
DMA_FGETA(DMA_ADDRH(h,##REG),##REG,##FIELD)
#define DMA_FSETH(h,REG,FIELD,x)\
DMA_FSETA(DMA_ADDRH(h,##REG),##REG,##FIELD,x)
#define DMA_FSETSH(h,REG,FIELD,SYM)\
DMA_FSETSA(DMA_ADDRH(h,##REG),##REG,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | A U X C T L |
* |___________________|
*
* AUXCTL - auxiliary control register
*
* FIELDS (msb -> lsb)
* (rw) AUXPRI
* (rw) CHPRI
*
\******************************************************************************/
#define _DMA_AUXCTL_ADDR 0x01840070u
#define _DMA_AUXCTL_AUXPRI_MASK 0x00000010u
#define _DMA_AUXCTL_AUXPRI_SHIFT 0x00000004u
#define DMA_AUXCTL_AUXPRI_DEFAULT 0x00000000u
#define DMA_AUXCTL_AUXPRI_OF(x) _VALUEOF(x)
#define DMA_AUXCTL_AUXPRI_CPU 0x00000000u
#define DMA_AUXCTL_AUXPRI_DMA 0x00000001u
#define _DMA_AUXCTL_CHPRI_MASK 0x0000000Fu
#define _DMA_AUXCTL_CHPRI_SHIFT 0x00000000u
#define DMA_AUXCTL_CHPRI_DEFAULT 0x00000000u
#define DMA_AUXCTL_CHPRI_OF(x) _VALUEOF(x)
#define DMA_AUXCTL_CHPRI_HIGHEST 0x00000000u
#define DMA_AUXCTL_CHPRI_2ND 0x00000001u
#define DMA_AUXCTL_CHPRI_3RD 0x00000002u
#define DMA_AUXCTL_CHPRI_4TH 0x00000003u
#define DMA_AUXCTL_CHPRI_LOWEST 0x00000004u
#define DMA_AUXCTL_OF(x) _VALUEOF(x)
#define DMA_AUXCTL_DEFAULT (Uint32)( \
_PER_FDEFAULT(DMA,AUXCTL,AUXPRI) \
|_PER_FDEFAULT(DMA,AUXCTL,CHPRI) \
)
#define DMA_AUXCTL_RMK(auxpri,chpri) (Uint32)( \
_PER_FMK(DMA,AUXCTL,AUXPRI,auxpri) \
|_PER_FMK(DMA,AUXCTL,CHPRI,chpri) \
)
#define _DMA_AUXCTL_FGET(FIELD)\
_PER_FGET(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD)
#define _DMA_AUXCTL_FSET(FIELD,field)\
_PER_FSET(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD,field)
#define _DMA_AUXCTL_FSETS(FIELD,SYM)\
_PER_FSETS(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | P R I C T L |
* |___________________|
*
* PRICTL0 - channel primary control register 0
* PRICTL1 - channel primary control register 1
* PRICTL2 - channel primary control register 2
* PRICTL3 - channel primary control register 3
*
* FIELDS (msb -> lsb)
* (rw) DSTRLD
* (rw) SRCRLD
* (rw) EMOD
* (rw) FS
* (rw) TCINT
* (rw) PRI
* (rw) WSYNC
* (rw) RSYNC
* (rw) INDEX
* (rw) CNTRLD
* (rw) SPLIT
* (rw) ESIZE
* (rw) DSTDIR
* (rw) SRCDIR
* (r) STATUS
* (rw) START
*
\******************************************************************************/
#define _DMA_PRICTL_OFFSET 0
#define _DMA_PRICTL0_ADDR 0x01840000u
#define _DMA_PRICTL1_ADDR 0x01840040u
#define _DMA_PRICTL2_ADDR 0x01840004u
#define _DMA_PRICTL3_ADDR 0x01840044u
#define _DMA_PRICTL_DSTRLD_MASK 0xC0000000u
#define _DMA_PRICTL_DSTRLD_SHIFT 0x0000001Eu
#define DMA_PRICTL_DSTRLD_DEFAULT 0x00000000u
#define DMA_PRICTL_DSTRLD_OF(x) _VALUEOF(x)
#define DMA_PRICTL_DSTRLD_NONE 0x00000000u
#define DMA_PRICTL_DSTRLD_B 0x00000001u
#define DMA_PRICTL_DSTRLD_C 0x00000002u
#define DMA_PRICTL_DSTRLD_D 0x00000003u
#define _DMA_PRICTL_SRCRLD_MASK 0x30000000u
#define _DMA_PRICTL_SRCRLD_SHIFT 0x0000001Cu
#define DMA_PRICTL_SRCRLD_DEFAULT 0x00000000u
#define DMA_PRICTL_SRCRLD_OF(x) _VALUEOF(x)
#define DMA_PRICTL_SRCRLD_NONE 0x00000000u
#define DMA_PRICTL_SRCRLD_B 0x00000001u
#define DMA_PRICTL_SRCRLD_C 0x00000002u
#define DMA_PRICTL_SRCRLD_D 0x00000003u
#define _DMA_PRICTL_EMOD_MASK 0x08000000u
#define _DMA_PRICTL_EMOD_SHIFT 0x0000001Bu
#define DMA_PRICTL_EMOD_DEFAULT 0x00000000u
#define DMA_PRICTL_EMOD_OF(x) _VALUEOF(x)
#define DMA_PRICTL_EMOD_NOHALT 0x00000000u
#define DMA_PRICTL_EMOD_HALT 0x00000001u
#define _DMA_PRICTL_FS_MASK 0x04000000u
#define _DMA_PRICTL_FS_SHIFT 0x0000001Au
#define DMA_PRICTL_FS_DEFAULT 0x00000000u
#define DMA_PRICTL_FS_OF(x) _VALUEOF(x)
#define DMA_PRICTL_FS_DISABLE 0x00000000u
#define DMA_PRICTL_FS_RSYNC 0x00000001u
#define _DMA_PRICTL_TCINT_MASK 0x02000000u
#define _DMA_PRICTL_TCINT_SHIFT 0x00000019u
#define DMA_PRICTL_TCINT_DEFAULT 0x00000000u
#define DMA_PRICTL_TCINT_OF(x) _VALUEOF(x)
#define DMA_PRICTL_TCINT_DISABLE 0x00000000u
#define DMA_PRICTL_TCINT_ENABLE 0x00000001u
#define _DMA_PRICTL_PRI_MASK 0x01000000u
#define _DMA_PRICTL_PRI_SHIFT 0x00000018u
#define DMA_PRICTL_PRI_DEFAULT 0x00000000u
#define DMA_PRICTL_PRI_OF(x) _VALUEOF(x)
#define DMA_PRICTL_PRI_CPU 0x00000000u
#define DMA_PRICTL_PRI_DMA 0x00000001u
#define _DMA_PRICTL_WSYNC_MASK 0x00F80000u
#define _DMA_PRICTL_WSYNC_SHIFT 0x00000013u
#define DMA_PRICTL_WSYNC_DEFAULT 0x00000000u
#define DMA_PRICTL_WSYNC_OF(x) _VALUEOF(x)
#define DMA_PRICTL_WSYNC_NONE 0x00000000u
#define DMA_PRICTL_WSYNC_TINT0 0x00000001u
#define DMA_PRICTL_WSYNC_TINT1 0x00000002u
#define DMA_PRICTL_WSYNC_SDINT 0x00000003u
#define DMA_PRICTL_WSYNC_EXTINT4 0x00000004u
#define DMA_PRICTL_WSYNC_EXTINT5 0x00000005u
#define DMA_PRICTL_WSYNC_EXTINT6 0x00000006u
#define DMA_PRICTL_WSYNC_EXTINT7 0x00000007u
#define DMA_PRICTL_WSYNC_DMAINT0 0x00000008u
#define DMA_PRICTL_WSYNC_DMAINT1 0x00000009u
#define DMA_PRICTL_WSYNC_DMAINT2 0x0000000Au
#define DMA_PRICTL_WSYNC_DMAINT3 0x0000000Bu
#define DMA_PRICTL_WSYNC_XEVT0 0x0000000Cu
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