📄 csl_mdiohal.h
字号:
* | USERINTMASKED |
* | USERINTMASKSET |
* | USERINTMASKCLEAR |
* |___________________|
*
* LINKINTRAW - Link Status Change Interrupt Register
* LINKINTMASKED - Link Status Change Interrupt Register (Masked)
* USERINTRAW - User Command Complete Interrupt
* USERINTMASKED - User Command Complete Interrupt (Masked)
* USERINTMASKSET - Enable User Command Complete Interrupt Mask
* USERINTMASKCLEAR - Disable User Command Complete Interrupt Mask
*
* FIELDS (msb -> lsb)
* MAC0 - Mac 0 Flag (yes/no)
* MAC1 - Mac 1 Flag (yes/no)
*
* MACROS SUPPORTED
* MDIO_FMK y
* MDIO_FMKS y
* MDIO_FMKMIF .
* MDIO_ADDR y
* MDIO_REG y
* MDIO_RGET y
* MDIO_RSET y
* MDIO_FGET y
* MDIO_FSET y
* MDIO_FSETS .
*
\******************************************************************************/
#define _MDIO_LINKINTRAW_ADDR (_MDIO_BASE_ADDR+0x0010u)
#define _MDIO_LINKINTMASKED_ADDR (_MDIO_BASE_ADDR+0x0014u)
#define _MDIO_USERINTRAW_ADDR (_MDIO_BASE_ADDR+0x0020u)
#define _MDIO_USERINTMASKED_ADDR (_MDIO_BASE_ADDR+0x0024u)
#define _MDIO_USERINTMASKSET_ADDR (_MDIO_BASE_ADDR+0x0028u)
#define _MDIO_USERINTMASKCLEAR_ADDR (_MDIO_BASE_ADDR+0x002Cu)
#define MDIO_LINKINTRAW MDIO_REG(LINKINT)
#define MDIO_LINKINTMASKED MDIO_REG(LINKINTMASKED)
#define MDIO_USERINTRAW MDIO_REG(USERINTRAW)
#define MDIO_USERINTMASKED MDIO_REG(USERINTMASKED)
#define MDIO_USERINTMASKSET MDIO_REG(USERINTMASKSET)
#define MDIO_USERINTMASKCLEAR MDIO_REG(USERINTMASKCLEAR)
#define _MDIO_LINKINTRAW_MAC0_MASK 0x00000001u
#define _MDIO_LINKINTRAW_MAC0_SHIFT 0u
#define _MDIO_LINKINTRAW_MAC1_MASK 0x00000002u
#define _MDIO_LINKINTRAW_MAC1_SHIFT 1u
#define MDIO_LINKINTRAW_MAC0_YES 1u
#define MDIO_LINKINTRAW_MAC0_NO 0u
#define MDIO_LINKINTRAW_MAC1_YES 1u
#define MDIO_LINKINTRAW_MAC1_NO 0u
#define _MDIO_LINKINTMASKED_MAC0_MASK 0x00000001u
#define _MDIO_LINKINTMASKED_MAC0_SHIFT 0u
#define _MDIO_LINKINTMASKED_MAC1_MASK 0x00000002u
#define _MDIO_LINKINTMASKED_MAC1_SHIFT 1u
#define MDIO_LINKINTMASKED_MAC0_YES 1u
#define MDIO_LINKINTMASKED_MAC0_NO 0u
#define MDIO_LINKINTMASKED_MAC1_YES 1u
#define MDIO_LINKINTMASKED_MAC1_NO 0u
#define _MDIO_USERINTRAW_MAC0_MASK 0x00000001u
#define _MDIO_USERINTRAW_MAC0_SHIFT 0u
#define _MDIO_USERINTRAW_MAC1_MASK 0x00000002u
#define _MDIO_USERINTRAW_MAC1_SHIFT 1u
#define MDIO_USERINTRAW_MAC0_YES 1u
#define MDIO_USERINTRAW_MAC0_NO 0u
#define MDIO_USERINTRAW_MAC1_YES 1u
#define MDIO_USERINTRAW_MAC1_NO 0u
#define _MDIO_USERINTMASKED_MAC0_MASK 0x00000001u
#define _MDIO_USERINTMASKED_MAC0_SHIFT 0u
#define _MDIO_USERINTMASKED_MAC1_MASK 0x00000002u
#define _MDIO_USERINTMASKED_MAC1_SHIFT 1u
#define MDIO_USERINTMASKED_MAC0_YES 1u
#define MDIO_USERINTMASKED_MAC0_NO 0u
#define MDIO_USERINTMASKED_MAC1_YES 1u
#define MDIO_USERINTMASKED_MAC1_NO 0u
#define _MDIO_USERINTMASKSET_MAC0_MASK 0x00000001u
#define _MDIO_USERINTMASKSET_MAC0_SHIFT 0u
#define _MDIO_USERINTMASKSET_MAC1_MASK 0x00000002u
#define _MDIO_USERINTMASKSET_MAC1_SHIFT 1u
#define MDIO_USERINTMASKSET_MAC0_YES 1u
#define MDIO_USERINTMASKSET_MAC0_NO 0u
#define MDIO_USERINTMASKSET_MAC1_YES 1u
#define MDIO_USERINTMASKSET_MAC1_NO 0u
#define _MDIO_USERINTMASKCLEAR_MAC0_MASK 0x00000001u
#define _MDIO_USERINTMASKCLEAR_MAC0_SHIFT 0u
#define _MDIO_USERINTMASKCLEAR_MAC1_MASK 0x00000002u
#define _MDIO_USERINTMASKCLEAR_MAC1_SHIFT 1u
#define MDIO_USERINTMASKCLEAR_MAC0_YES 1u
#define MDIO_USERINTMASKCLEAR_MAC0_NO 0u
#define MDIO_USERINTMASKCLEAR_MAC1_YES 1u
#define MDIO_USERINTMASKCLEAR_MAC1_NO 0u
/******************************************************************************\
* _____________________
* | |
* | USERACCESS0 |
* | USERACCESS1 |
* |___________________|
*
* USERACCESS0 - User Access Register 0
* USERACCESS1 - User Access Register 1
*
* FIELDS (msb -> lsb)
* (rws) GO - Go Bit
* (rw) WRITE - Write Enable
* (r) ACK - Acknowledge
* (rw) REGADR - PHY Register Address
* (rw) PHYADR - PHY Device Address
* (rw) DATA - User Data to Read/Write
*
* MACROS SUPPORTED
* MDIO_FMK y
* MDIO_FMKS .
* MDIO_FMKMIF .
* MDIO_ADDR y
* MDIO_REG y
* MDIO_RGET y
* MDIO_RSET y
* MDIO_FGET y
* MDIO_FSET y
* MDIO_FSETS .
*
\******************************************************************************/
#define _MDIO_USERACCESS0_ADDR (_MDIO_BASE_ADDR+0x0080u)
#define _MDIO_USERACCESS1_ADDR (_MDIO_BASE_ADDR+0x0088u)
#define MDIO_USERACCESS0 MDIO_REG(USERACCESS0)
#define MDIO_USERACCESS1 MDIO_REG(USERACCESS1)
#define _MDIO_USERACCESS0_GO_MASK 0x80000000u
#define _MDIO_USERACCESS0_GO_SHIFT 31u
#define _MDIO_USERACCESS0_WRITE_MASK 0x40000000u
#define _MDIO_USERACCESS0_WRITE_SHIFT 30u
#define _MDIO_USERACCESS0_ACK_MASK 0x20000000u
#define _MDIO_USERACCESS0_ACK_SHIFT 29u
#define _MDIO_USERACCESS0_REGADR_MASK 0x03E00000u
#define _MDIO_USERACCESS0_REGADR_SHIFT 21u
#define _MDIO_USERACCESS0_PHYADR_MASK 0x001F0000u
#define _MDIO_USERACCESS0_PHYADR_SHIFT 16u
#define _MDIO_USERACCESS0_DATA_MASK 0x0000FFFFu
#define _MDIO_USERACCESS0_DATA_SHIFT 0u
#define _MDIO_USERACCESS1_GO_MASK 0x80000000u
#define _MDIO_USERACCESS1_GO_SHIFT 31u
#define _MDIO_USERACCESS1_WRITE_MASK 0x40000000u
#define _MDIO_USERACCESS1_WRITE_SHIFT 30u
#define _MDIO_USERACCESS1_ACK_MASK 0x20000000u
#define _MDIO_USERACCESS1_ACK_SHIFT 29u
#define _MDIO_USERACCESS1_REGADR_MASK 0x03E00000u
#define _MDIO_USERACCESS1_REGADR_SHIFT 21u
#define _MDIO_USERACCESS1_PHYADR_MASK 0x001F0000u
#define _MDIO_USERACCESS1_PHYADR_SHIFT 16u
#define _MDIO_USERACCESS1_DATA_MASK 0x0000FFFFu
#define _MDIO_USERACCESS1_DATA_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | USERPHYSEL0 |
* | USERPHYSEL1 |
* |___________________|
*
* USERPHYSEL0 - User PHY Select Register 0
* USERPHYSEL1 - User PHY Select Register 1
*
* FIELDS (msb -> lsb)
* (rw) LINKSEL - Link Detect Type Selection
* (rw) LINKINTENB - Link Interrupt Enable
* (rw) PHYADDR - Address (0-31) of Phy to Use
*
* MACROS SUPPORTED
* MDIO_FMK y
* MDIO_FMKS y
* MDIO_FMKMIF .
* MDIO_ADDR y
* MDIO_REG y
* MDIO_RGET y
* MDIO_RSET y
* MDIO_FGET y
* MDIO_FSET y
* MDIO_FSETS y
*
\******************************************************************************/
#define _MDIO_USERPHYSEL0_ADDR (_MDIO_BASE_ADDR+0x0084u)
#define _MDIO_USERPHYSEL1_ADDR (_MDIO_BASE_ADDR+0x008Cu)
#define MDIO_USERPHYSEL0 MDIO_REG(USERPHYSEL0)
#define MDIO_USERPHYSEL1 MDIO_REG(USERPHYSEL1)
#define _MDIO_USERPHYSEL0_LINKSEL_MASK 0x00000080u
#define _MDIO_USERPHYSEL0_LINKSEL_SHIFT 7u
#define MDIO_USERPHYSEL0_LINKSEL_MLINK 1u
#define MDIO_USERPHYSEL0_LINKSEL_MDIO 0u
#define _MDIO_USERPHYSEL0_LINKINTENB_MASK 0x00000040u
#define _MDIO_USERPHYSEL0_LINKINTENB_SHIFT 6u
#define MDIO_USERPHYSEL0_LINKINTENB_ENABLE 1u
#define MDIO_USERPHYSEL0_LINKINTENB_DISABLE 0u
#define _MDIO_USERPHYSEL0_PHYADDR_MASK 0x0000001Fu
#define _MDIO_USERPHYSEL0_PHYADDR_SHIFT 0u
#define _MDIO_USERPHYSEL1_LINKSEL_MASK 0x00000080u
#define _MDIO_USERPHYSEL1_LINKSEL_SHIFT 7u
#define MDIO_USERPHYSEL1_LINKSEL_MLINK 1u
#define MDIO_USERPHYSEL1_LINKSEL_MDIO 0u
#define _MDIO_USERPHYSEL1_LINKINTENB_MASK 0x00000040u
#define _MDIO_USERPHYSEL1_LINKINTENB_SHIFT 6u
#define MDIO_USERPHYSEL1_LINKINTENB_ENABLE 1u
#define MDIO_USERPHYSEL1_LINKINTENB_DISABLE 0u
#define _MDIO_USERPHYSEL1_PHYADDR_MASK 0x0000001Fu
#define _MDIO_USERPHYSEL1_PHYADDR_SHIFT 0u
#endif /* MDIO_SUPPORT */
#endif /* _CSL_MDIOHAL_H_ */
/******************************************************************************\
* End of csl_mdiohal.h
\******************************************************************************/
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