📄 csl_edmahal.h
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/*****************************************************************************\
* Copyright (C) 1999-2000 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_edmahal.h
* DATE CREATED.. 06/12/1999
* LAST MODIFIED. 06/17/2003 6712C
* 05/28/2003 6711C
* 2/22/2002 DM642
*------------------------------------------------------------------------------
* REGISTERS/PARAMETERS
*
* OPT - options parameter
* SRC - source address parameter
* CNT - transfer count parameter
* DST - destination address parameter
* IDX - index parameter
* RLD - count reload + link parameter
* QOPT - QDMA options register
* QSRC - QDMA source address register
* QCNT - QDMA transfer count register
* QDST - QDMA destination address register
* QIDX - QDMA index register
* QSOPT - QDMA options pseudo register
* QSSRC - QDMA source address pseudo register
* QSCNT - QDMA transfer count pseudo register
* QSDST - QDMA destination address pseudo register
* QSIDX - QDMA index pseudo register
* PQSR - priority queue status register
* PQAR0 - priority queue allocation register 0
* PQAR1 - priority queue allocation register 1
* PQAR2 - priority queue allocation register 2
* PQAR3 - priority queue allocation register 3
* CIPR - channel interrupt pending register
* CIPRL - channel interrupt pending register, low half (1)
* CIPRH - channel interrupt pending register, high half (1)
* CIER - channel interrupt enable register
* CIERL - channel interrupt enable register, low half (1)
* CIERH - channel interrupt enable register, high half (1)
* CCER - channel chain enable register
* CCERL - channel chain enable register, low half (1)
* CCERH - channel chain enable register, high half (1)
* ER - event register
* ERL - event register, low half (1)
* ERH - event register, high half (1)
* EER - event enable register
* EERL - event enable register, low half (1)
* EERH - event enable register, high half (1)
* EPRL - event polarity register, low half (1)
* EPRH - event polarity register, high half (1)
* ECR - event clear register
* ECRL - event clear register, low half (1)
* ECRH - event clear register, high half (1)
* ESR - event set register
* ESRL - event set register, low half (1)
* ESRH - event set register, high half (1)
*
*
* CHIP_6713, CHIP_DA610, CHIP_6711C and CHIP_6712C
* ESEL0 - event selection register 0 (2)
* ESEL1 - event selection register 1 (2)
* ESEL2 - event selection register 2 (2) (3)
* ESEL3 - event selection register 3 (2)
*
* (1) - only supported on C64x devices
* (2) - only supported on C6713, DA610, 6711C and 6712C
* (3) - the whole register is reserved
\******************************************************************************/
#ifndef _CSL_EDMAHAL_H
#define _CSL_EDMAHAL_H_
#include <csl_stdinc.h>
#include <csl_chip.h>
#if (EDMA_SUPPORT)
/******************************************************************************\
* MISC section
\******************************************************************************/
#if (CHIP_6414 | CHIP_6415 | CHIP_6416 | CHIP_6411 )
#define _EDMA_CHA_CNT 64
#define _EDMA_BASE_PRAM 0x01A00000u
#define _EDMA_PRAM_START _EDMA_BASE_PRAM
#define _EDMA_PRAM_SIZE 0x00000800u
#define _EDMA_PRAM_ERASE 0x00000600u
#endif
#if (CHIP_DM642 | CHIP_6412)
#define _EDMA_CHA_CNT 64
#define _EDMA_BASE_PRAM 0x01A00000u
#define _EDMA_PRAM_START _EDMA_BASE_PRAM
#define _EDMA_PRAM_SIZE 0x00001400u
#define _EDMA_PRAM_ERASE 0x00000600u
#endif
#if (CHIP_6211 | CHIP_6711 | CHIP_6712 | CHIP_6713 | CHIP_DA610 | CHIP_6711C | CHIP_6712C)
#define _EDMA_CHA_CNT 16
#define _EDMA_BASE_PRAM 0x01A00000u
#define _EDMA_PRAM_START _EDMA_BASE_PRAM
#define _EDMA_PRAM_SIZE 0x00000800u
#define _EDMA_PRAM_ERASE 0x00000180u
#endif
#define _EDMA_ENTRY_SIZE 0x00000018u
#define _EDMA_NULL_PARAM (_EDMA_PRAM_START+_EDMA_ENTRY_SIZE*_EDMA_CHA_CNT)
#define _EDMA_RSVD_PARAM (_EDMA_NULL_PARAM+_EDMA_ENTRY_SIZE)
#define _EDMA_LINK_START (_EDMA_RSVD_PARAM+_EDMA_ENTRY_SIZE)
#define _EDMA_LINK_CNT ((_EDMA_PRAM_SIZE/_EDMA_ENTRY_SIZE)-(_EDMA_CHA_CNT+2))
#define _EDMA_SCRATCH_START (_EDMA_LINK_START+_EDMA_LINK_CNT*_EDMA_ENTRY_SIZE)
#define _EDMA_SCRATCH_SIZE (_EDMA_PRAM_START+_EDMA_PRAM_SIZE-_EDMA_SCRATCH_START)
/******************************************************************************\
* module level register/field access macros
\******************************************************************************/
/* ----------------- */
/* FIELD MAKE MACROS */
/* ----------------- */
#define EDMA_FMK(REG,FIELD,x)\
_PER_FMK(EDMA,##REG,##FIELD,x)
#define EDMA_FMKS(REG,FIELD,SYM)\
_PER_FMKS(EDMA,##REG,##FIELD,##SYM)
/* -------------------------------- */
/* RAW REGISTER/FIELD ACCESS MACROS */
/* -------------------------------- */
#define EDMA_REG(REG) (*(volatile Uint32*)(_EDMA_##REG##_ADDR))
#define EDMA_ADDR(REG)\
_EDMA_##REG##_ADDR
#define EDMA_RGET(REG)\
_PER_RGET(_EDMA_##REG##_ADDR,EDMA,##REG)
#define EDMA_RSET(REG,x)\
_PER_RSET(_EDMA_##REG##_ADDR,EDMA,##REG,x)
#define EDMA_FGET(REG,FIELD)\
_EDMA_##REG##_FGET(##FIELD)
#define EDMA_FSET(REG,FIELD,x)\
_EDMA_##REG##_FSET(##FIELD,##x)
#define EDMA_FSETS(REG,FIELD,SYM)\
_EDMA_##REG##_FSETS(##FIELD,##SYM)
/* ------------------------------------------ */
/* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */
/* ------------------------------------------ */
#define EDMA_RGETA(addr,REG)\
_PER_RGET(addr,EDMA,##REG)
#define EDMA_RSETA(addr,REG,x)\
_PER_RSET(addr,EDMA,##REG,x)
#define EDMA_FGETA(addr,REG,FIELD)\
_PER_FGET(addr,EDMA,##REG,##FIELD)
#define EDMA_FSETA(addr,REG,FIELD,x)\
_PER_FSET(addr,EDMA,##REG,##FIELD,x)
#define EDMA_FSETSA(addr,REG,FIELD,SYM)\
_PER_FSETS(addr,EDMA,##REG,##FIELD,##SYM)
/* ----------------------------------------- */
/* HANDLE BASED REGISTER/FIELD ACCESS MACROS */
/* ----------------------------------------- */
#define EDMA_ADDRH(h,REG)\
((((Uint32)(h))&0x0000FFFF)+_EDMA_PRAM_START+(_EDMA_##REG##_OFFSET<<2))
#define EDMA_RGETH(h,REG)\
EDMA_RGETA(EDMA_ADDRH(h,##REG),##REG)
#define EDMA_RSETH(h,REG,x)\
EDMA_RSETA(EDMA_ADDRH(h,##REG),##REG,x)
#define EDMA_FGETH(h,REG,FIELD)\
EDMA_FGETA(EDMA_ADDRH(h,##REG),##REG,##FIELD)
#define EDMA_FSETH(h,REG,FIELD,x)\
EDMA_FSETA(EDMA_ADDRH(h,##REG),##REG,##FIELD,x)
#define EDMA_FSETSH(h,REG,FIELD,SYM)\
EDMA_FSETSA(EDMA_ADDRH(h,##REG),##REG,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | O P T |
* | Q O P T |
* | Q S O P T |
* |___________________|
*
* OPT - options parameter
* QOPT - QDMA options register
* QSOPT - QDMA options pseudo register
*
* FIELDS (msb -> lsb)
* (rw) PRI
* (rw) ESIZE
* (rw) 2DS
* (rw) SUM
* (rw) 2DD
* (rw) DUM
* (rw) TCINT
* (rw) TCC
* (rw) TCCM (1)
* (rw) ATCINT (1)
* (rw) ATCC (1)
* (rw) PDTS (1)
* (rw) PDTD (1)
* (rw) LINK
* (rw) FS
*
* (1) - only supported on C64x devices
*
\******************************************************************************/
#define _EDMA_OPT_OFFSET 0
#define _EDMA_QOPT_OFFSET 0
#define _EDMA_QSOPT_OFFSET 8
#define _EDMA_QOPT_ADDR 0x02000000u
#define _EDMA_QSOPT_ADDR 0x02000020u
#define EDMA_QOPT EDMA_REG(QOPT)
#define EDMA_QSOPT EDMA_REG(QSOPT)
#define _EDMA_OPT_PRI_MASK 0xE0000000u
#define _EDMA_OPT_PRI_SHIFT 0x0000001Du
#define EDMA_OPT_PRI_DEFAULT 0x00000000u
#define EDMA_OPT_PRI_OF(x) _VALUEOF(x)
#if (C64_SUPPORT)
#define EDMA_OPT_PRI_URGENT 0x00000000u
#define EDMA_OPT_PRI_HIGH 0x00000001u
#define EDMA_OPT_PRI_MEDIUM 0x00000002u
#define EDMA_OPT_PRI_LOW 0x00000003u
#else
#define EDMA_OPT_PRI_HIGH 0x00000001u
#define EDMA_OPT_PRI_LOW 0x00000002u
#endif
#define _EDMA_OPT_ESIZE_MASK 0x18000000u
#define _EDMA_OPT_ESIZE_SHIFT 0x0000001Bu
#define EDMA_OPT_ESIZE_DEFAULT 0x00000000u
#define EDMA_OPT_ESIZE_OF(x) _VALUEOF(x)
#define EDMA_OPT_ESIZE_32BIT 0x00000000u
#define EDMA_OPT_ESIZE_16BIT 0x00000001u
#define EDMA_OPT_ESIZE_8BIT 0x00000002u
#define _EDMA_OPT_2DS_MASK 0x04000000u
#define _EDMA_OPT_2DS_SHIFT 0x0000001Au
#define EDMA_OPT_2DS_DEFAULT 0x00000000u
#define EDMA_OPT_2DS_OF(x) _VALUEOF(x)
#define EDMA_OPT_2DS_NO 0x00000000u
#define EDMA_OPT_2DS_YES 0x00000001u
#define _EDMA_OPT_SUM_MASK 0x03000000u
#define _EDMA_OPT_SUM_SHIFT 0x00000018u
#define EDMA_OPT_SUM_DEFAULT 0x00000000u
#define EDMA_OPT_SUM_OF(x) _VALUEOF(x)
#define EDMA_OPT_SUM_NONE 0x00000000u
#define EDMA_OPT_SUM_INC 0x00000001u
#define EDMA_OPT_SUM_DEC 0x00000002u
#define EDMA_OPT_SUM_IDX 0x00000003u
#define _EDMA_OPT_2DD_MASK 0x00800000u
#define _EDMA_OPT_2DD_SHIFT 0x00000017u
#define EDMA_OPT_2DD_DEFAULT 0x00000000u
#define EDMA_OPT_2DD_OF(x) _VALUEOF(x)
#define EDMA_OPT_2DD_NO 0x00000000u
#define EDMA_OPT_2DD_YES 0x00000001u
#define _EDMA_OPT_DUM_MASK 0x00600000u
#define _EDMA_OPT_DUM_SHIFT 0x00000015u
#define EDMA_OPT_DUM_DEFAULT 0x00000000u
#define EDMA_OPT_DUM_OF(x) _VALUEOF(x)
#define EDMA_OPT_DUM_NONE 0x00000000u
#define EDMA_OPT_DUM_INC 0x00000001u
#define EDMA_OPT_DUM_DEC 0x00000002u
#define EDMA_OPT_DUM_IDX 0x00000003u
#define _EDMA_OPT_TCINT_MASK 0x00100000u
#define _EDMA_OPT_TCINT_SHIFT 0x00000014u
#define EDMA_OPT_TCINT_DEFAULT 0x00000000u
#define EDMA_OPT_TCINT_OF(x) _VALUEOF(x)
#define EDMA_OPT_TCINT_NO 0x00000000u
#define EDMA_OPT_TCINT_YES 0x00000001u
#define _EDMA_OPT_TCC_MASK 0x000F0000u
#define _EDMA_OPT_TCC_SHIFT 0x00000010u
#define EDMA_OPT_TCC_DEFAULT 0x00000000u
#define EDMA_OPT_TCC_OF(x) _VALUEOF(x)
#if (C64_SUPPORT)
#define _EDMA_OPT_TCCM_MASK 0x00006000u
#define _EDMA_OPT_TCCM_SHIFT 0x0000000Du
#define EDMA_OPT_TCCM_DEFAULT 0x00000000u
#define EDMA_OPT_TCCM_OF(x) _VALUEOF(x)
#define _EDMA_OPT_ATCINT_MASK 0x00001000u
#define _EDMA_OPT_ATCINT_SHIFT 0x0000000Cu
#define EDMA_OPT_ATCINT_DEFAULT 0x00000000u
#define EDMA_OPT_ATCINT_OF(x) _VALUEOF(x)
#define EDMA_OPT_ATCINT_NO 0x00000000u
#define EDMA_OPT_ATCINT_YES 0x00000001u
#define _EDMA_OPT_ATCC_MASK 0x000007E0u
#define _EDMA_OPT_ATCC_SHIFT 0x00000005u
#define EDMA_OPT_ATCC_DEFAULT 0x00000000u
#define EDMA_OPT_ATCC_OF(x) _VALUEOF(x)
#define _EDMA_OPT_PDTS_MASK 0x00000008u
#define _EDMA_OPT_PDTS_SHIFT 0x00000003u
#define EDMA_OPT_PDTS_DEFAULT 0x00000000u
#define EDMA_OPT_PDTS_OF(x) _VALUEOF(x)
#define EDMA_OPT_PDTS_DISABLE 0x00000000u
#define EDMA_OPT_PDTS_ENABLE 0x00000001u
#define _EDMA_OPT_PDTD_MASK 0x00000004u
#define _EDMA_OPT_PDTD_SHIFT 0x00000002u
#define EDMA_OPT_PDTD_DEFAULT 0x00000000u
#define EDMA_OPT_PDTD_OF(x) _VALUEOF(x)
#define EDMA_OPT_PDTD_DISABLE 0x00000000u
#define EDMA_OPT_PDTD_ENABLE 0x00000001u
#endif
#define _EDMA_OPT_LINK_MASK 0x00000002u
#define _EDMA_OPT_LINK_SHIFT 0x00000001u
#define EDMA_OPT_LINK_DEFAULT 0x00000000u
#define EDMA_OPT_LINK_OF(x) _VALUEOF(x)
#define EDMA_OPT_LINK_NA 0x00000000u
#define EDMA_OPT_LINK_NO 0x00000000u
#define EDMA_OPT_LINK_YES 0x00000001u
#define _EDMA_OPT_FS_MASK 0x00000001u
#define _EDMA_OPT_FS_SHIFT 0x00000000u
#define EDMA_OPT_FS_DEFAULT 0x00000000u
#define EDMA_OPT_FS_OF(x) _VALUEOF(x)
#define EDMA_OPT_FS_NO 0x00000000u
#define EDMA_OPT_FS_YES 0x00000001u
#define EDMA_OPT_OF(x) _VALUEOF(x)
#if (C64_SUPPORT)
#define EDMA_OPT_DEFAULT (Uint32)(\
_PER_FDEFAULT(EDMA,OPT,PRI)\
|_PER_FDEFAULT(EDMA,OPT,ESIZE)\
|_PER_FDEFAULT(EDMA,OPT,2DS)\
|_PER_FDEFAULT(EDMA,OPT,SUM)\
|_PER_FDEFAULT(EDMA,OPT,2DD)\
|_PER_FDEFAULT(EDMA,OPT,DUM)\
|_PER_FDEFAULT(EDMA,OPT,TCINT)\
|_PER_FDEFAULT(EDMA,OPT,TCC)\
|_PER_FDEFAULT(EDMA,OPT,TCCM)\
|_PER_FDEFAULT(EDMA,OPT,ATCINT) \
|_PER_FDEFAULT(EDMA,OPT,ATCC) \
|_PER_FDEFAULT(EDMA,OPT,PDTS) \
|_PER_FDEFAULT(EDMA,OPT,PDTD) \
|_PER_FDEFAULT(EDMA,OPT,LINK)\
|_PER_FDEFAULT(EDMA,OPT,FS)\
)
#define EDMA_OPT_RMK(pri,esize,ds2,sum,dd2,dum,tcint,tcc,tccm,atcint,atcc,\
pdts,pdtd,link,fs) (Uint32)(\
_PER_FMK(EDMA,OPT,PRI,pri) \
|_PER_FMK(EDMA,OPT,ESIZE,esize) \
|_PER_FMK(EDMA,OPT,2DS,ds2) \
|_PER_FMK(EDMA,OPT,SUM,sum) \
|_PER_FMK(EDMA,OPT,2DD,dd2) \
|_PER_FMK(EDMA,OPT,DUM,dum) \
|_PER_FMK(EDMA,OPT,TCINT,tcint) \
|_PER_FMK(EDMA,OPT,TCC,tcc) \
|_PER_FMK(EDMA,OPT,TCCM,tccm) \
|_PER_FMK(EDMA,OPT,ATCINT,atcint) \
|_PER_FMK(EDMA,OPT,ATCC,atcc) \
|_PER_FMK(EDMA,OPT,PDTS,pdts) \
|_PER_FMK(EDMA,OPT,PDTD,pdtd) \
|_PER_FMK(EDMA,OPT,LINK,link) \
|_PER_FMK(EDMA,OPT,FS,fs) \
)
#endif
#if (!C64_SUPPORT)
#define EDMA_OPT_DEFAULT (Uint32)(\
_PER_FDEFAULT(EDMA,OPT,PRI)\
|_PER_FDEFAULT(EDMA,OPT,ESIZE)\
|_PER_FDEFAULT(EDMA,OPT,2DS)\
|_PER_FDEFAULT(EDMA,OPT,SUM)\
|_PER_FDEFAULT(EDMA,OPT,2DD)\
|_PER_FDEFAULT(EDMA,OPT,DUM)\
|_PER_FDEFAULT(EDMA,OPT,TCINT)\
|_PER_FDEFAULT(EDMA,OPT,TCC)\
|_PER_FDEFAULT(EDMA,OPT,LINK)\
|_PER_FDEFAULT(EDMA,OPT,FS)\
)
#define EDMA_OPT_RMK(pri,esize,ds2,sum,dd2,dum,tcint,tcc,link,fs) (Uint32)(\
_PER_FMK(EDMA,OPT,PRI,pri) \
|_PER_FMK(EDMA,OPT,ESIZE,esize) \
|_PER_FMK(EDMA,OPT,2DS,ds2) \
|_PER_FMK(EDMA,OPT,SUM,sum) \
|_PER_FMK(EDMA,OPT,2DD,dd2) \
|_PER_FMK(EDMA,OPT,DUM,dum) \
|_PER_FMK(EDMA,OPT,TCINT,tcint) \
|_PER_FMK(EDMA,OPT,TCC,tcc) \
|_PER_FMK(EDMA,OPT,LINK,link) \
|_PER_FMK(EDMA,OPT,FS,fs) \
)
#endif
#define _EDMA_QOPT_FGET(FIELD)\
_PER_FGET(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD)
#define _EDMA_QOPT_FSET(FIELD,field)\
_PER_FSET(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD,field)
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