📄 c8051f060.inc
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;---------------------------------------------------------------------------
;
;
;
;
; FILE NAME: C8051F060.INC
; TARGET MCUs: C8051F060, F061, F062, F063
; DESCRIPTION: Register/bit definitions for the C8051F060 product family.
;
; REVISION 1.2
;
;---------------------------------------------------------------------------
;REGISTER DEFINITIONS
;
P0 DATA 080H ; PORT 0 LATCH
SP DATA 081H ; STACK POINTER
DPL DATA 082H ; DATA POINTER LOW
DPH DATA 083H ; DATA POINTER HIGH
SFRPAGE DATA 084H ; SFR PAGE REGISTER
SFRNEXT DATA 085H ; SFR PAGE REGISTER
SFRLAST DATA 086H ; SFR PAGE STACK ACCESS REGISTER
PCON DATA 087H ; POWER CONTROL
CPT0CN DATA 088H ; COMPARATOR 0 CONTROL
CPT1CN DATA 088H ; COMPARATOR 1 CONTROL
CPT2CN DATA 088H ; COMPARATOR 2 CONTROL
TCON DATA 088H ; TIMER/COUNTER CONTROL
CPT0MD DATA 089H ; COMPARATOR 0 CONFIGURATION
CPT1MD DATA 089H ; COMPARATOR 1 CONFIGURATION
CPT2MD DATA 089H ; COMPARATOR 2 CONFIGURATION
TMOD DATA 089H ; TIMER/COUNTER MODE
OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL
TL0 DATA 08AH ; TIMER/COUNTER 0 LOW
OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION
TL1 DATA 08BH ; TIMER/COUNTER 1 LOW
OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL
TH0 DATA 08CH ; TIMER/COUNTER 0 HIGH
TH1 DATA 08DH ; TIMER/COUNTER 1 HIGH
CKCON DATA 08EH ; CLOCK CONTROL
PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
P1 DATA 090H ; PORT 1 LATCH
SSTA0 DATA 091H ; UART 0 STATUS
SFRPGCN DATA 096H ; SFR PAGE CONTROL REGISTER
CLKSEL DATA 097H ; OSCILLATOR CLOCK SELECTION REGISTER
SCON0 DATA 098H ; UART 0 CONTROL
SCON1 DATA 098H ; UART 1 CONTROL
SBUF0 DATA 099H ; UART 0 DATA BUFFER
SBUF1 DATA 099H ; UART 1 DATA BUFFER
SPI0CFG DATA 09AH ; SPI CONFIGURATION
SPI0DAT DATA 09BH ; SPI DATA
P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE CONFIGURATION
P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE CONFIGURATION
SPI0CKR DATA 09DH ; SPI CLOCK RATE CONTROL
P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE CONFIGURATION
P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE CONFIGURATION
P2 DATA 0A0H ; PORT 2 LATCH
EMI0TC DATA 0A1H ; EMIF TIMING CONTROL
EMI0CN DATA 0A2H ; EMIF CONTROL
EMI0CF DATA 0A3H ; EMIF CONFIGURATION
P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION
P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION
P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION
P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION
IE DATA 0A8H ; INTERRUPT ENABLE
SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS
P1MDIN DATA 0ADH ; PORT 1 INPUT MODE
P2MDIN DATA 0AEH ; PORT 2 INPUT MODE
P3 DATA 0B0H ; PORT 3 LATCH
FLACL DATA 0B7H ; FLASH ACCESS LIMIT
FLSCL DATA 0B7H ; FLASH SCALE
IP DATA 0B8H ; INTERRUPT PRIORITY
SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS ENABLE
ADC0CPT DATA 0BAH ; ADC0 CALIBRATION POINTER
AMX2CF DATA 0BAH ; ADC2 ANALOG MULTIPLEXER CONFIGURATION
ADC0CCF DATA 0BBH ; ADC0 CALIBRATION COEFFICIENT
AMX0SL DATA 0BBH ; ADC0 MULTIPLEXER CHANNEL SELECT
AMX2SL DATA 0BBH ; ADC2 ANALOG MULTIPLEXER CHANNEL SELECT
ADC0CF DATA 0BCH ; ADC0 CONFIGURATION
ADC1CF DATA 0BCH ; ADC1 CONFIGURATION
ADC2CF DATA 0BCH ; ADC2 CONFIGURATION
ADC0L DATA 0BEH ; ADC0 DATA WORD LOW
ADC1L DATA 0BEH ; ADC1 DATA WORD LOW
ADC2L DATA 0BEH ; ADC2 DATA WORD LOW
ADC0H DATA 0BFH ; ADC0 DATA WORD HIGH
ADC1H DATA 0BFH ; ADC1 DATA WORD HIGH
ADC2H DATA 0BFH ; ADC2 DATA WORD HIGH
CAN0STA DATA 0C0H ; CAN0 STATUS
SMB0CN DATA 0C0H ; SMBUS CONTROL
SMB0STA DATA 0C1H ; SMBUS STATUS
SMB0DAT DATA 0C2H ; SMBUS DATA
SMB0ADR DATA 0C3H ; SMBUS SLAVE ADDRESS
ADC0GTL DATA 0C4H ; ADC0 GREATER-THAN LOW
ADC2GTL DATA 0C4H ; ADC2 GREATER-THAN LOW
ADC0GTH DATA 0C5H ; ADC0 GREATER-THAN HIGH
ADC2GTH DATA 0C5H ; ADC2 GREATER-THAN HIGH
ADC0LTL DATA 0C6H ; ADC0 LESS-THAN LOW
ADC2LTL DATA 0C6H ; ADC2 LESS-THAN LOW
ADC0LTH DATA 0C7H ; ADC0 LESS-THAN HIGH
ADC2LTH DATA 0C7H ; ADC2 LESS-THAN HIGH
P4 DATA 0C8H ; PORT 4 LATCH
TMR2CN DATA 0C8H ; TIMER/COUNTER 2 CONTROL
TMR3CN DATA 0C8H ; TIMER/COUNTER 3 CONTROL
TMR4CN DATA 0C8H ; TIMER/COUNTER 4 CONTROL
TMR2CF DATA 0C9H ; TIMER/COUNTER 2 CONFIGURATION
TMR3CF DATA 0C9H ; TIMER/COUNTER 3 CONFIGURATION
TMR4CF DATA 0C9H ; TIMER/COUNTER 4 CONFIGURATION
RCAP2L DATA 0CAH ; TIMER/COUNTER 2 CAPTURE/RELOAD LOW
RCAP3L DATA 0CAH ; TIMER/COUNTER 3 CAPTURE/RELOAD LOW
RCAP4L DATA 0CAH ; TIMER/COUNTER 4 CAPTURE/RELOAD LOW
RCAP2H DATA 0CBH ; TIMER/COUNTER 2 CAPTURE/RELOAD HIGH
RCAP3H DATA 0CBH ; TIMER/COUNTER 3 CAPTURE/RELOAD HIGH
RCAP4H DATA 0CBH ; TIMER/COUNTER 4 CAPTURE/RELOAD HIGH
TMR2L DATA 0CCH ; TIMER/COUNTER 2 LOW
TMR3L DATA 0CCH ; TIMER/COUNTER 3 LOW
TMR4L DATA 0CCH ; TIMER/COUNTER 4 LOW
TMR2H DATA 0CDH ; TIMER/COUNTER 2 HIGH
TMR3H DATA 0CDH ; TIMER/COUNTER 3 HIGH
TMR4H DATA 0CDH ; TIMER/COUNTER 4 HIGH
SMB0CR DATA 0CFH ; SMBUS CLOCK RATE
PSW DATA 0D0H ; PROGRAM STATUS WORD
REF0CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 0
REF1CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 1
REF2CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL 2
DAC0L DATA 0D2H ; DAC0 LOW
DAC1L DATA 0D2H ; DAC1 LOW
DAC0H DATA 0D3H ; DAC0 HIGH
DAC1H DATA 0D3H ; DAC1 HIGH
DAC0CN DATA 0D4H ; DAC0 CONTROL
DAC1CN DATA 0D4H ; DAC1 CONTROL
CAN0DATL DATA 0D8H ; CAN0 DATA LOW
DMA0CN DATA 0D8H ; DMA0 CONTROL
P5 DATA 0D8H ; PORT 5 LATCH
PCA0CN DATA 0D8H ; PCA CONTROL
CAN0DATH DATA 0D9H ; CAN0 DATA HIGH
DMA0DAL DATA 0D9H ; DMA0 DATA ADDRESS BEGINNING LOW BYTE
PCA0MD DATA 0D9H ; PCA MODE
CAN0ADR DATA 0DAH ; CAN0 ADDRESS
DMA0DAH DATA 0DAH ; DMA0 DATA ADDRESS BEGINNING HIGH BYTE
PCA0CPM0 DATA 0DAH ; PCA MODULE 0 MODE REGISTER
CAN0TST DATA 0DBH ; CAN0 TEST
DMA0DSL DATA 0DBH ; DMA0 DATA ADDRESS POINTER LOW BYTE
PCA0CPM1 DATA 0DBH ; PCA MODULE 1 MODE REGISTER
DMA0DSH DATA 0DCH ; DMA0 DATA ADDRESS POINTER HIGH BYTE
PCA0CPM2 DATA 0DCH ; PCA MODULE 2 MODE REGISTER
DMA0IPT DATA 0DDH ; DMA0 INSTRUCTION WRITE ADDRESS
PCA0CPM3 DATA 0DDH ; PCA MODULE 3 MODE REGISTER
DMA0IDT DATA 0DEH ; DMA0 INSTRUCTION WRITE DATA
PCA0CPM4 DATA 0DEH ; PCA MODULE 4 MODE REGISTER
PCA0CPM5 DATA 0DFH ; PCA MODULE 5 MODE REGISTER
ACC DATA 0E0H ; ACCUMULATOR
PCA0CPL5 DATA 0E1H ; PCA CAPTURE 5 LOW
XBR0 DATA 0E1H ; PORT I/O CROSSBAR CONTROL 0
PCA0CPH5 DATA 0E2H ; PCA CAPTURE 5 HIGH
XBR1 DATA 0E2H ; PORT I/O CROSSBAR CONTROL 1
XBR2 DATA 0E3H ; PORT I/O CROSSBAR CONTROL 2
XBR3 DATA 0E4H ; PORT I/O CROSSBAR CONTROL 3
EIE1 DATA 0E6H ; EXTENDED INTERRUPT ENABLE 1
EIE2 DATA 0E7H ; EXTENDED INTERRUPT ENABLE 2
ADC0CN DATA 0E8H ; ADC0 CONTROL
ADC1CN DATA 0E8H ; ADC1 CONTROL
ADC2CN DATA 0E8H ; ADC2 CONTROL
P6 DATA 0E8H ; PORT 6 LATCH
PCA0CPL2 DATA 0E9H ; PCA CAPTURE 2 LOW
PCA0CPH2 DATA 0EAH ; PCA CAPTURE 2 HIGH
PCA0CPL3 DATA 0EBH ; PCA CAPTURE 3 LOW
PCA0CPH3 DATA 0ECH ; PCA CAPTURE 3 HIGH
PCA0CPL4 DATA 0EDH ; PCA CAPTURE 4 LOW
PCA0CPH4 DATA 0EEH ; PCA CAPTURE 4 HIGH
RSTSRC DATA 0EFH ; RESET SOURCE
B DATA 0F0H ; B REGISTER
EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1
EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY 2
CAN0CN DATA 0F8H ; CAN0 CONTROL
DMA0CF DATA 0F8H ; DMA0 CONFIGURATION
P7 DATA 0F8H ; PORT 7 LATCH
SPI0CN DATA 0F8H ; SPI CONTROL
DMA0CTL DATA 0F9H ; DMA0 REPEAT COUNTER LIMIT LOW BYTE
PCA0L DATA 0F9H ; PCA COUNTER LOW
DMA0CTH DATA 0FAH ; DMA0 REPEAT COUNTER LIMIT HIGH BYTE
PCA0H DATA 0FAH ; PCA COUNTER HIGH
DMA0CSL DATA 0FBH ; DMA0 REPEAT COUNTER STATUS LOW BYTE
PCA0CPL0 DATA 0FBH ; PCA CAPTURE 0 LOW
DMA0CSH DATA 0FCH ; DMA0 REPEAT COUNTER STATUS HIGH BYTE
PCA0CPH0 DATA 0FCH ; PCA CAPTURE 0 HIGH
DMA0BND DATA 0FDH ; DMA0 INSTRUCTION BOUNDARY
PCA0CPL1 DATA 0FDH ; PCA CAPTURE 1 LOW
DMA0ISW DATA 0FEH ; DMA0 INSTRUCTION STATUS
PCA0CPH1 DATA 0FEH ; PCA CAPTURE 1 HIGH
WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL
;
;------------------------------------------------------------------------------
;BIT DEFINITIONS
;
; TCON 088H
TF1 BIT 08FH ; TIMER 1 OVERFLOW FLAG
TR1 BIT 08EH ; TIMER 1 ON/OFF CONTROL
TF0 BIT 08DH ; TIMER 0 OVERFLOW FLAG
TR0 BIT 08CH ; TIMER 0 ON/OFF CONTROL
IE1 BIT 08BH ; EXT. INTERRUPT 1 EDGE FLAG
IT1 BIT 08AH ; EXT. INTERRUPT 1 TYPE
IE0 BIT 089H ; EXT. INTERRUPT 0 EDGE FLAG
IT0 BIT 088H ; EXT. INTERRUPT 0 TYPE
; CPT0CN 088H
CP0EN BIT 08FH ; COMPARATOR 0 ENABLE
CP0OUT BIT 08EH ; COMPARATOR 0 OUTPUT
CP0RIF BIT 08DH ; COMPARATOR 0 RISING EDGE INTERRUPT
CP0FIF BIT 08CH ; COMPARATOR 0 FALLING EDGE INTERRUPT
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