m3s028ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// TDM Serial Port
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.009

// Revision history
// V1.009 - 27 June 1997
//          Tri-state drivers removed.

// m3s028ct
// M320C50 TDM Serial Port Control.
// Provides TX and Rx clocks and TDM serial port control signals.
//
// TDMRegCntrl:
//    0 : TRCV write
//    1 : TDXR write
//    2 : TSPC write
//    3 : TCSR write
//    4 : TRTA write
//    5 : TRAD write (This register is actually read only)
//    6 : TRCV read
//    7 : TDXR read
//    8 : TSPC read
//    9 : TCSR read
//   10 : TRTA read
//   11 : TRAD read
//


module m3s028ct (Clock, Reset, TDMRegCntrl, MMRWriteData,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    TCLKXI, TCLKR, TDX, NTDXE, TDR, TFSXI, TFSXO, NTFSXE, TFSR, TADD, NTADDE,
    TCLKX, NTCLKXE, TRNT, TXNT, PMMRRdData);

    input        Clock, Reset;
    input [11:0] TDMRegCntrl;
    input [15:0] MMRWriteData;
    input        TCLKXI, TCLKR, TDR, TFSXI, TFSR;
    output       TDX, NTDXE, TFSXO, NTFSXE, TADD, NTADDE, TCLKX, NTCLKXE;
    output [15:0] PMMRRdData;
    output        TRNT, TXNT;

    reg [13:0] TSPC, NextTSPC;
    reg  [7:0] TCSR, NextTCSR, TCSRSave, RxAddr, TxAddr;
    reg [15:0] TRTA, NextTRTA;
    reg        NTFSXE, TFSX, NTADDE, TFSXO, NTCLKXE;
    reg        TxReset, RxReset;
    reg        RxClockDis1, RxClockDis2;
    reg        RxData, RxFSR, FrameSync;
    reg  [2:0] LastRxSlot;
    reg        TDMTxFs, TDMRxFs;
    reg        EndRxSlot, EndTxSlot;
    reg [15:0] PMMRRdData;

    wire [15:0] NextTRCV, NextTDXR;
    wire        TCLKX, TADD, TRNT, TXNT, NTDXE, TxFSO;
    wire  [3:0] RxCount, TxCount;
    wire        RxRdy, TxRdy, TxRegNotEmpty, RxSRFull;
    wire        TDMRxValid;
    wire        TxClock, RxClock, NTxClock, NRxClock;
    wire  [7:0] TRADSave;
    wire  [2:0] RxSlot;
    wire  [2:0] TxSlot;


// TSPC register
always @(TDMRegCntrl or MMRWriteData or TSPC or TCLKXI or TCLKR 
         or RxRdy or TxRdy or TxRegNotEmpty or RxSRFull)
begin
    if (TDMRegCntrl[2]) NextTSPC[7:0] = MMRWriteData[7:0];
    else begin
        NextTSPC[0] = TSPC[0];
        NextTSPC[2:1] = {TSPC[2] & ~NextTSPC[0], TSPC[1] & ~NextTSPC[0]};
        NextTSPC[7:3] = TSPC[7:3];
    end

    NextTSPC[13:8] = {RxSRFull,TxRegNotEmpty,TxRdy,RxRdy,TCLKXI,TCLKR};
end

// TCSR, TRTA registers
always @(TDMRegCntrl or MMRWriteData or TCSR or TRTA)
begin
    if (TDMRegCntrl[3]) NextTCSR = MMRWriteData[7:0];
    else NextTCSR = TCSR;

    if (TDMRegCntrl[4]) NextTRTA = MMRWriteData[15:0];
    else NextTRTA = TRTA;
end

// Update registers
always @(posedge Clock or posedge Reset)
begin
    if (Reset) TSPC[7:0] <= 8'b0;
    else TSPC <= NextTSPC;
end
always @(posedge Clock)
begin
    TCSR <= NextTCSR;
    TRTA <= NextTRTA;
end
always @(TSPC)
begin
   TxReset = TSPC[6];
   RxReset = TSPC[7];
end

// Transmitter
m3s029ct U1 (Clock, TxClock, NTxClock, TxReset, MMRWriteData, TDMRegCntrl[1],
      TSPC[0], TSPC[2], TSPC[3], TSPC[5], TDMTxFs, TxFSO, TDX, NTDXE, TxRegNotEmpty,
      TxRdy, NextTDXR, TXNT, TxCount, TxSlot, TCSRSave);

// Receiver
// TxClock used to latch data during TDM mode.
m3s030ct U2 (Clock, RxClock, NRxClock, RxReset, TxClock, MMRWriteData, TDMRegCntrl[0], TDMRegCntrl[6],
     RxData, TDMRxFs, TSPC[0], TSPC[2], TSPC[3], RxSRFull, RxRdy, TDMRxValid, RxCount,
     NextTRCV, TRNT, RxSlot);

// Clock disable signals
always @(posedge Clock or posedge Reset)
begin
    if (Reset)
    begin
        RxClockDis1 <= 0;
        RxClockDis2 <= 0;
    end
    else
    begin
        RxClockDis1 <= ~TSPC[7] & ~TSPC[4];
        RxClockDis2 <= RxClockDis1;
    end
end

// Tx clock output enable
always @(negedge Clock or posedge Reset)
begin
    if (Reset) NTCLKXE <= 1;
    else NTCLKXE <= ~TSPC[4];
end

// Clock Generator
m3s034ct U5 (Clock, TCLKXI, TCLKR, NTCLKXE, TSPC[1], RxClockDis2,
    TCLKX, TxClock, NTxClock, RxClock, NRxClock);

// Frame sync control
always @(TSPC or TFSXI)
begin
    NTFSXE = ~TSPC[5];
    TFSX = TFSXI;
end

// Digital Loopback mode
always @(TSPC or TFSR or TDR or TDX or TFSX)
begin
    if (TSPC[1]) begin
        RxData = TDX;
        RxFSR = TFSX;
    end
    else begin
        RxData = TDR;
        RxFSR = TFSR;
    end
end

// Generate TDM frame pulse
always @(posedge TxClock)
begin
    FrameSync <= ((TxCount == 15) && (TxSlot == 7));
end

// Frame sync output
always @(TSPC or FrameSync or TxFSO)
begin
    TFSXO = ((FrameSync & TSPC[0]) | (TxFSO & ~TSPC[0]));
end

// TDM transmit address
m3s031ct U3 (TxClock, TxCount, TxAddr, TADD);

// TDM receive address
m3s032ct U4 (RxReset, TSPC[0], RxClock, TxClock, RxAddr,
             RxCount, TFSR, TDMRxValid, TRADSave);

// Detect last TDM slot
always @(RxCount or RxSlot)
begin
    EndRxSlot = ((RxCount == 10) && (RxSlot == 7));
end
always @(TxCount or TxSlot)
begin
    EndTxSlot = ((TxCount == 10) && (TxSlot == 7));
end

// Latch Tx/Rx addresses, channel select
always @(posedge TxClock or negedge TxReset)
begin
    if (~TxReset) begin
        TxAddr <= 0;
        TCSRSave <= 0;
    end
    else begin
        if (EndTxSlot) begin
            TxAddr <= TRTA[15:8];
            TCSRSave <= TCSR;
        end
    end
end
always @(posedge RxClock or negedge RxReset)
begin
    if (~RxReset) RxAddr <= 0;
    else if (EndRxSlot) RxAddr <= TRTA[7:0];
end

// TDM frame sync signals
always @(TSPC or TFSXI or RxFSR)
begin
    TDMTxFs = TFSXI;
    TDMRxFs = (TFSXI  & TSPC[0]) | (RxFSR & ~TSPC[0]);
end

// Save last valid receive slot
always @(posedge RxClock or posedge Reset)
begin
    if (Reset) LastRxSlot <= 3'b0;
    else if ((RxCount == 15) && TDMRxValid) LastRxSlot <= RxSlot;
end

// TDM Address output enables
always @(NTDXE or TSPC)
begin
    NTADDE = (NTDXE | ~TSPC[0]);
end

// PMMRRdData output mux
always @(TDMRegCntrl or NextTRCV or NextTDXR or NextTSPC or NextTCSR or NextTRTA or
    RxSlot or LastRxSlot or TRADSave)
    if (TDMRegCntrl[6]) PMMRRdData = NextTRCV;
    else if (TDMRegCntrl[7]) PMMRRdData = NextTDXR;
    else if (TDMRegCntrl[8]) PMMRRdData = {2'b0,NextTSPC};
    else if (TDMRegCntrl[9]) PMMRRdData = {8'b0,NextTCSR};
    else if (TDMRegCntrl[10]) PMMRRdData = NextTRTA;
    else if (TDMRegCntrl[11]) PMMRRdData = {2'b0,RxSlot,LastRxSlot,TRADSave};
    else PMMRRdData = 0;

endmodule