m3s024ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Timer
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.201

// Revision history
// V1.201 - 27 June 1997
//          Tri-state drivers removed.
// V1.2   - 15 May 1996
//          Timer interrupt disabled if timer disabled.
// V1.100 - 10 May 1996

// m3s024ct
// M320C50 Timer Counter.
//
// TimRegCntrl:
//    0 : TIM write
//    1 : PRD write
//    2 : TCR write
//    3 : TIM read
//    4 : PRD read
//    5 : TCR read
//
// The load of the TDDR bits in TCR is delayed by 1 clock cycle.

`define C_TIM_RESET 16'hFFFF
`define C_PRD_RESET 16'hFFFF
`define C_TCR_RESET 16'h0000


module m3s024ct (Clock, Reset, TimRegCntrl, MMRWriteData,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    TINT, TOUT, PMMRRdData);
    input        Clock, Reset;
    input  [5:0] TimRegCntrl;
    input [15:0] MMRWriteData;
    output [15:0] PMMRRdData;
    output        TINT, TOUT;

    reg [15:0] TIM, PRD, NextTIM, SourceTIM, NextPRD, PMMRRdData;
    reg  [9:0] TCR, NextTCR;
    reg        TSS, TRB, TINT, TOUT;
    reg        TimerBorrow, PreScaleBorrow;
    reg        TimerEnab, TimerReload, LoadTDDR, TINTDel;
    reg  [3:0] TDDRData, TDDR, PSC;

// Delay TDDR load
always @(posedge Clock)
   TDDRData <= MMRWriteData[3:0];

always @(posedge Clock or posedge Reset)
if (Reset)
    LoadTDDR <= 0;
else
    LoadTDDR <= TimRegCntrl[2];

// Timer Registers
always @(TimRegCntrl or MMRWriteData or TDDRData or TimerEnab or TimerReload
     or TIM or PRD or TCR or TimerBorrow or PreScaleBorrow or LoadTDDR)
begin
    if (TimRegCntrl[0]) SourceTIM = MMRWriteData;
    else SourceTIM = TIM;
    if (TimerReload | ((TimerBorrow & PreScaleBorrow) & ~TimRegCntrl[0])) NextTIM = PRD;
    else if (TimerEnab & PreScaleBorrow) NextTIM = SourceTIM - 1;
    else NextTIM = SourceTIM;

    if (TimRegCntrl[1]) NextPRD = MMRWriteData;
    else NextPRD = PRD;

    if (LoadTDDR) TDDR = TDDRData;
    else TDDR = TCR[3:0];
    if (TimRegCntrl[2]) TSS = MMRWriteData[4];
    else TSS = TCR[4];
    if (TimRegCntrl[2]) TRB = MMRWriteData[5];
    else TRB = 0;
    if (~TimerEnab) PSC = TCR[9:6];
    else if (TimerReload | PreScaleBorrow) PSC = TCR[3:0];
    else PSC = TCR[9:6] - 1;
    NextTCR = {PSC,TRB,TSS,TDDR};
end
always @(posedge Clock or posedge Reset)
if (Reset)
begin
    TIM <= `C_TIM_RESET;
    PRD <= `C_PRD_RESET;
    TCR <= `C_TCR_RESET;
end
else
begin
    TIM <= NextTIM;
    PRD <= NextPRD;
    TCR <= NextTCR;
end

// Timer control signals
always @(posedge Clock)
begin
    TimerEnab <= ~TCR[4];
    TimerReload <= TCR[5];
end

// Timer and prescaler borrow signals
always @(TIM or TCR or TimerEnab)
begin
    TimerBorrow = (TIM == 0) & TimerEnab;
    PreScaleBorrow = (TCR[9:6] == 0);
end

// Timer interrupt
always @(TimerBorrow or PreScaleBorrow)
    TINT = TimerBorrow & PreScaleBorrow;

// Tout derived from TINT
always @(posedge Clock)
begin
    TINTDel <= TINT;
    TOUT <= TINTDel;
end

// PMMRRdData output mux
always @(TimRegCntrl or NextTIM or NextPRD or NextTCR)
    if (TimRegCntrl[3]) PMMRRdData = NextTIM;
    else if (TimRegCntrl[4]) PMMRRdData = NextPRD;
    else if (TimRegCntrl[5]) PMMRRdData = {6'b0,NextTCR};
    else PMMRRdData = 0;

endmodule