m3s049ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Data Address Latches
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.001

// m3s049ct
// M320C50 Latches for use with data addressing.
// These latches, together with the MemCycle control line are in a
// separate block to prevent the synthesiser from mixing MemCycle with
// the decoding logic.

module m3s049ct (Clock, Reset, MemCycle,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  NextReadAddr, NextWriteAddr, NextDataPage, NextRdPortAddr,
  NextIORdRq, NextDpRdRq, NextSpRdRq, NextExRdRq, NextMMRdRq,
  NextIOWrRq, NextDpWrRq, NextSpWrRq, NextExWrRq, NextMMWrRq,
  ReadAddr, WriteAddr, DataPage, RdPortAddr,
  IORdRq, DpRdRq, SpRdRq, ExRdRq, MMRdRq,
  IOWrRq, DpWrRq, SpWrRq, ExWrRq, MMWrRq);

    input         Clock, Reset, MemCycle;
    input  [15:0] NextReadAddr, NextWriteAddr, NextRdPortAddr;
    input   [8:0] NextDataPage;
    input   [2:0] NextDpRdRq, NextDpWrRq;
    input         NextIORdRq, NextSpRdRq, NextExRdRq, NextMMRdRq;
    input         NextIOWrRq, NextSpWrRq, NextExWrRq, NextMMWrRq;
    output [15:0] ReadAddr, WriteAddr, RdPortAddr;
    output  [8:0] DataPage;
    output  [2:0] DpRdRq, DpWrRq;
    output        IORdRq, SpRdRq, ExRdRq, MMRdRq;
    output        IOWrRq, SpWrRq, ExWrRq, MMWrRq;

    reg [15:0] ReadAddr, WriteAddr, RdPortAddr;
    reg  [8:0] DataPage;
    reg  [2:0] DpRdRq, DpWrRq;
    reg        IORdRq, SpRdRq, ExRdRq, MMRdRq;
    reg        IOWrRq, SpWrRq, ExWrRq, MMWrRq;


always @(posedge Clock)
if (MemCycle)
begin
    ReadAddr <= NextReadAddr;
    WriteAddr <= NextWriteAddr;
    RdPortAddr <= NextRdPortAddr;
    DataPage <= NextDataPage;
end

always @(posedge Clock or posedge Reset)
if (Reset)
begin
    IORdRq <= 0;
    DpRdRq <= 0;
    SpRdRq <= 0;
    ExRdRq <= 0;
    MMRdRq <= 0;
    IOWrRq <= 0;
    DpWrRq <= 0;
    SpWrRq <= 0;
    ExWrRq <= 0;
    MMWrRq <= 0;
end
else if (MemCycle)
begin
    IORdRq <= NextIORdRq;
    DpRdRq <= NextDpRdRq;
    SpRdRq <= NextSpRdRq;
    ExRdRq <= NextExRdRq;
    MMRdRq <= NextMMRdRq;
    IOWrRq <= NextIOWrRq;
    DpWrRq <= NextDpWrRq;
    SpWrRq <= NextSpWrRq;
    ExWrRq <= NextExWrRq;
    MMWrRq <= NextMMWrRq;
end

endmodule