m3s025ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Serial Port
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.007

// Revision history
// V1.007 - 27 June 1997
//          Tri-state drivers removed.

// m3s025ct
// M320C50 Serial Port Control.
// Provides TX and Rx clocks and serial port control signals.
//
// SPRegCntrl:
//    0 : DRR write
//    1 : DXR write
//    2 : SPC write
//    3 : DRR read
//    4 : DXR read
//    5 : SPC read
//
// A bidirect buffer is required on the TxClock output to feed
// the internally generated clock back into CLKXI when NCLKXE is low.


module m3s025ct (Clock, Reset, SPRegCntrl, MMRWriteData,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    CLKXI, CLKR, DX, NDXE, DR, FSXI, FSXO, NFSXE, FSR,
    TCLKX, NCLKXE, RINT, XINT, PMMRRdData);
    input        Clock, Reset;
    input  [5:0] SPRegCntrl;
    input [15:0] MMRWriteData;
    input        CLKXI, CLKR, DR, FSXI, FSR;
    output       DX, NDXE, FSXO, NFSXE, TCLKX, NCLKXE;
    output [15:0] PMMRRdData;
    output        RINT, XINT;

    reg [13:0] SPC, NextSPC;
    reg        NFSXE, FSX, NCLKXE;
    reg        RxClockDis1, RxClockDis2;
    reg        RxData, RxFSR;
    reg [15:0] PMMRRdData;

    wire [15:0] NextDRR, NextDXR;
    wire        TxClock, RxClock, NTxClock, NRxClock;
    wire        TCLKX, FSXO, RINT, XINT;
    wire        RxRdy, TxRdy, TxRegNotEmpty, RxSRFull;


// SPC register
always @(SPRegCntrl or MMRWriteData or SPC or CLKXI or CLKR or RxRdy
         or TxRdy or TxRegNotEmpty or RxSRFull)
begin
  if (SPRegCntrl[2]) NextSPC[7:0] = MMRWriteData[7:0];
  else NextSPC[7:0] = SPC[7:0];

  NextSPC[13:8] = {RxSRFull,TxRegNotEmpty,TxRdy,RxRdy,CLKXI,CLKR};
end
always @(posedge Clock or posedge Reset)
begin
    if (Reset) SPC[7:0] <= 8'b0;
    else SPC <= NextSPC;
end

// Clock disable signals
always @(posedge Clock or posedge Reset)
begin
    if (Reset) begin
        RxClockDis1 <= 0;
        RxClockDis2 <= 0;
    end
    else begin
        RxClockDis1 <= ~SPC[7] & ~SPC[4];
        RxClockDis2 <= RxClockDis1;
    end
end

// Tx Clock output enable
always @(negedge Clock or posedge Reset)
begin
    if (Reset) NCLKXE <= 1;
    else NCLKXE <= ~SPC[4];
end

// Clock Generator
m3s033ct U3 (Clock, CLKXI, CLKR, NCLKXE, SPC[1], RxClockDis2,
    TCLKX, TxClock, NTxClock, RxClock, NRxClock);

// Transmitter
m3s026ct U1 (Clock, TxClock, NTxClock, SPC[6], MMRWriteData, SPRegCntrl[1],
      SPC[2], SPC[3], SPC[5], FSXI,
      FSXO, DX, NDXE, TxRegNotEmpty, TxRdy, NextDXR, XINT);

// Receiver
m3s027ct U2 (Clock, RxClock, NRxClock, SPC[7], MMRWriteData, SPRegCntrl[0], SPRegCntrl[3],
     RxData, RxFSR, SPC[2], SPC[3], RxSRFull, RxRdy, NextDRR, RINT);

// Frame sync control
always @(SPC or FSXI)
begin
    NFSXE = ~SPC[5];
    FSX = FSXI;
end

// Digital Loopback mode
always @(SPC or FSR or DR or DX or FSX)
begin
    if (SPC[1]) begin
        RxData = DX;
        RxFSR = FSX;
    end
    else begin
        RxData = DR;
        RxFSR = FSR;
    end
end

// PMMRRdData output mux
always @(SPRegCntrl or NextDRR or NextDXR or NextSPC)
    if (SPRegCntrl[3]) PMMRRdData = NextDRR;
    else if (SPRegCntrl[4]) PMMRRdData = NextDXR;
    else if (SPRegCntrl[5]) PMMRRdData = {2'b0,NextSPC};
    else PMMRRdData = 0;

endmodule