m3s014ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// External Memory Controller
// Copyright Mentor Graphics Corporation and Licensors 1998. 
// V1.104

// m3s014ct
// M320C50 External memory controller.
// Provides address and control signals for the external memory.
// One wait state is added to write cycles.
// An idle cycle follows all write cycles, this has no affect on write cycles
// but a read cycle can not occur during an idle cycle.
// All memory accesses can be extended by driving the ERdy input low.
// If program writes, program reads, data writes, or data reads want to access the memory
// then the accesses are done sequentially with the following priority:
// data writes, then program writes, then program  reads, then data reads.
//
// GAddrEnab are the contents of the GREG register.
// ExtAccEnab is the external access enable signal (low during bus hold mode).
// MemAccEnab is the memory access enable signal (low during idle modes).


module m3s014ct (ProgAddr, WriteAddr, ReadAddr, 
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    PrRdReq, PrWrReq, DaWrReq, DaRdReq, IOWrReq, IORdReq,
    ERdy, WriteReady, MemCycle, FClock, Clock, Reset, GAddrEnab,
    ExtAccEnab, MemAccEnab, AVIS, PACntrl14, PACntrl7,
    OA, NDS, NPS, NIS, NWR, NRD, ExPmRdy, ExDmRdy, ExWrRdy,
    ExDataValid, ExProgValid, NDEN, NBR, ODRegEnab, RNWO, NSTRBO,
    DWAccess, DRAccess, PAccess, IWAccess, IRAccess);
    input  [15:0] ProgAddr, WriteAddr, ReadAddr;
    input         PrRdReq, PrWrReq, DaWrReq, DaRdReq, IOWrReq, IORdReq;
    input         ERdy, WriteReady, MemCycle, FClock, Clock, Reset;
    input   [7:0] GAddrEnab;
    input         ExtAccEnab, MemAccEnab, AVIS, PACntrl14, PACntrl7;
    output [15:0] OA;
    output        NDS, NPS, NIS, NWR, NRD, ExPmRdy, ExDmRdy, ExWrRdy;
    output        ExDataValid, ExProgValid, NDEN, NBR, ODRegEnab;
    output        RNWO, NSTRBO;
    output        DWAccess, DRAccess, PAccess, IWAccess, IRAccess;

    reg [15:0] NextWrAddrDel, WrAddrDel, LastAddr, OA;
    reg NDS, NPS, NIS, NWR, NRD, ExPmRdy, ExDmRdy, ExWrRdy;
    reg ExDataValid, ExProgValid, NDEN, NBR, ODRegEnab, NoPrgRead, AVISDel;
    reg PrRdCycle, PrWrCycle, DaWrCycle, DaRdCycle;
    reg PrRdActive, PrWrActive, DaWrActive, DaRdActive;
    reg DaWrCycRdy, DaRdCycRdy, PrRdCycRdy, PrWrCycRdy, IdleCycle;
    reg DaWrConflict, DaRdConflict, PrRdConflict, PrWrConflict;
    reg DaWrWait, PrWrWait, DaWrActDel, PrWrActDel, IOWrActDel, WrActDel;
    reg DWAccess, DRAccess, PAccess, IWAccess, IRAccess;
    reg RNWO, NSTRBO, StartCyc, DaRdAddrSel, PrAddrSel, LastAddrSel, HoldAddr;

// Latch write address
always @(PrWrActive or DaWrActive or ProgAddr or WriteAddr)
    NextWrAddrDel = (ProgAddr & {16{PrWrActive}})
                  | (WriteAddr & {16{DaWrActive}});
always @(posedge FClock)
    if (Clock)
        WrAddrDel <= NextWrAddrDel;

// Delay AVIS bit and latch PACntrl7
always @(posedge Clock)
begin
    AVISDel <= AVIS;
    if (MemCycle)
        NoPrgRead <= PACntrl7;
end

// Address multiplexer
always @(AVISDel or NoPrgRead or DaWrActive or PrWrActive)
    HoldAddr = (AVISDel | NoPrgRead | DaWrActive | PrWrActive);
always @(DaRdReq or IORdReq or DaWrReq or IOWrReq or PrRdReq or PrWrReq
    or DaRdCycle or DaWrCycle or PrRdCycle or PrWrCycle or IdleCycle)
    DaRdAddrSel = (DaRdReq | IORdReq) & DaRdCycle &
          ~(IdleCycle | ((DaWrReq | IOWrReq) & DaWrCycle) |
            (PrWrReq & PrWrCycle) | (PrRdReq & PrRdCycle));
always @(PrRdReq or PrWrReq or DaWrReq or IOWrReq or PrRdCycle or PrWrCycle
    or DaWrCycle or IdleCycle or HoldAddr or WrActDel or DaRdAddrSel)
    PrAddrSel = (PrRdReq & PrRdCycle &
          ~(IdleCycle | ((DaWrReq | IOWrReq) & DaWrCycle) |
            (PrWrReq & PrWrCycle))) | 
          ~(HoldAddr | WrActDel | DaRdAddrSel);
always @(HoldAddr or WrActDel or DaRdAddrSel or PrRdReq or PrRdCycle
    or IdleCycle or DaWrReq or IOWrReq or PrWrReq or DaWrCycle or PrWrCycle)
    LastAddrSel = HoldAddr &
        ~(WrActDel | DaRdAddrSel | (PrRdReq & PrRdCycle &
          ~(IdleCycle | ((DaWrReq | IOWrReq) & DaWrCycle) |
           (PrWrReq & PrWrCycle))));
always @(WrActDel or DaRdAddrSel or PrAddrSel or LastAddrSel
     or ProgAddr or WrAddrDel or ReadAddr or LastAddr)
    OA = (WrAddrDel & {16{WrActDel}}) |
         (ReadAddr & {16{DaRdAddrSel}}) |
         (ProgAddr & {16{PrAddrSel}}) |
         (LastAddr & {16{LastAddrSel}});

// Address latch
always @(posedge Clock)
    LastAddr <= OA;

// Wait state generators
always @(posedge Clock or posedge Reset)
begin
    if (Reset)
    begin
        DaWrWait <= 0;
        PrWrWait <= 0;
    end
    else
    begin
        if (MemCycle) DaWrWait <= 1;
        else if ((~(DaWrReq | IOWrReq) | DaWrActive) & ExtAccEnab) DaWrWait <= 0;
        if (MemCycle) PrWrWait <= 1;
        else if ((~PrWrReq | PrWrActive) & ExtAccEnab) PrWrWait <= 0;
    end
end

// Ready output signals
always @(DaRdCycRdy or PrRdCycRdy or PrWrCycRdy
    or ERdy or DaWrWait or DaRdReq or DaWrReq or IORdReq or IOWrReq
    or PrRdReq or PrWrReq
    or DaRdConflict or PrRdConflict or PrWrConflict
    or DaWrActive or PrWrActive or DaWrWait or PrWrWait)
begin
    ExDmRdy = ~(((DaRdReq | IORdReq) & ~ERdy)
               | ((DaWrReq | IOWrReq) & (DaWrWait | ~ERdy))
               | DaRdConflict);
    ExPmRdy = ~((PrRdReq & ~ERdy) | (PrWrReq & (PrWrWait | ~ERdy))
               | (PrRdConflict | PrWrConflict));
    ExWrRdy = ~((DaWrActive | PrWrActive) & (~ERdy | DaWrWait | PrWrWait));
end

// Read data valid signal
always @(DaRdActive or WriteReady)
     ExDataValid = DaRdActive & WriteReady;

// Read program valid signal
always @(PrRdActive or WriteReady or PACntrl14)
     ExProgValid = PrRdActive & (WriteReady | ~PACntrl14);

// Cycle controller
always @(DaWrActive or PrRdActive or DaWrReq or DaRdReq or PrWrReq or PrRdReq
    or IOWrReq or IORdReq or PrWrActive or PrRdCycle or PrWrCycle or DaWrCycle
    or ERdy or PrWrWait or DaWrWait or IdleCycle or WriteReady or ExtAccEnab)
begin
    DaWrConflict = (DaWrReq | IOWrReq) & ~ExtAccEnab;
    PrWrConflict = PrWrReq & (((DaWrReq | IOWrReq) & DaWrCycle) | ~ExtAccEnab);
    PrRdConflict = PrRdReq & (((DaWrReq | IOWrReq) & DaWrCycle) |
                              (PrWrReq & PrWrCycle) | IdleCycle | ~ExtAccEnab);
    DaRdConflict = (DaRdReq | IORdReq) & (((DaWrReq | IOWrReq) & DaWrCycle) |
                              (PrRdReq & PrRdCycle) |
                              (PrWrReq & PrWrCycle) | IdleCycle | ~ExtAccEnab);
    DaWrCycRdy = ~(~ERdy | DaWrConflict | (DaWrWait & (DaWrReq | IOWrReq)));
    DaRdCycRdy = ~(~ERdy | ~WriteReady | DaRdConflict);
    PrWrCycRdy = ~(~ERdy | PrWrConflict | (PrWrWait & PrWrReq));
    PrRdCycRdy = ~(~ERdy | ~WriteReady | PrRdConflict);
end
     
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        DaWrCycle <= 0;
        DaRdCycle <= 0;
        PrWrCycle <= 0;
        PrRdCycle <= 0;
        IdleCycle <= 0;
    end
    else
    begin
        DaWrCycle <= MemCycle | (DaWrCycle & ~DaWrCycRdy);
        DaRdCycle <= MemCycle | (DaRdCycle & ~DaRdCycRdy);
        PrWrCycle <= MemCycle | (PrWrCycle & ~PrWrCycRdy);
        PrRdCycle <= MemCycle | (PrRdCycle & ~PrRdCycRdy);
        IdleCycle <= DaWrActive | PrWrActive;
    end

// Access control
always @(DaWrReq or IOWrReq or DaWrCycle or DaWrConflict)
    DaWrActive = (DaWrReq | IOWrReq) & DaWrCycle & ~DaWrConflict;
always @(PrWrReq or PrWrCycle or PrWrConflict)
    PrWrActive = PrWrReq & PrWrCycle & ~PrWrConflict;
always @(PrRdReq or PrRdCycle or PrRdConflict)
    PrRdActive = PrRdReq & PrRdCycle & ~PrRdConflict;
always @(DaRdReq or IORdReq or DaRdCycle or DaRdConflict)
    DaRdActive = (DaRdReq | IORdReq) & DaRdCycle & ~DaRdConflict;

// Memory control signals
always @(PrRdActive or PrWrActDel or DaWrActDel or DaRdActive or
     IOWrActDel or DaRdReq or IORdReq or MemAccEnab)
begin
    NPS = ~((PrWrActDel | PrRdActive) & MemAccEnab);
    NDS = ~((DaWrActDel | (DaRdActive & DaRdReq)) & MemAccEnab);
    NIS = ~((IOWrActDel | (DaRdActive & IORdReq)) & MemAccEnab);
end
always @(posedge FClock or posedge Reset)
    if (Reset)
    begin
        StartCyc <= 0;
        DaWrActDel <= 0;
        PrWrActDel <= 0;
        IOWrActDel <= 0;
        WrActDel <= 0;
        NRD <= 1;
        NDEN <= 1;
    end
    else
    begin
        StartCyc <= MemCycle & ~Clock;
        DaWrActDel <= DaWrActive & DaWrReq;
        IOWrActDel <= DaWrActive & IOWrReq;
        PrWrActDel <= PrWrActive;
        WrActDel <= DaWrActive | PrWrActive;
        NDEN <= ~((DaWrActive | PrWrActive) & ~StartCyc & MemAccEnab);
        if ((PrRdActive | DaRdActive) & (Clock | ~ERdy) & MemAccEnab)
            NRD <= 0;
        else
            NRD <= 1;
    end
always @(posedge Clock or posedge Reset)
    if (Reset)
        NWR <= 1;
    else if (((PrWrActive & (PrWrWait | ~ERdy))
           | (DaWrActive & (DaWrWait | ~ERdy))) & MemAccEnab)
        NWR <= 0;
    else
        NWR <= 1;

// RNW output signal
always @(negedge Clock)
    RNWO <= ~(DaWrActive | PrWrActive);

// NSTRB output signal
always @(NWR or DaRdActive or PrRdActive or MemAccEnab)
    NSTRBO = ~((~NWR | DaRdActive | PrRdActive) & MemAccEnab);

// Output data latch enable
always @(DaWrActive or PrWrActive)
    ODRegEnab = DaWrActive | PrWrActive;

// Global access control
always @(NDS or OA or GAddrEnab)
    if (~NDS & GAddrEnab[7] & OA[15] & ((GAddrEnab[6:0] & ~OA[14:8]) == 0))
        NBR = 0;
    else
        NBR = 1;

// Wait state generator control signals
always @(PrWrActive or PrRdActive or DaWrCycle or DaRdCycle
   or DaWrReq or DaRdReq or IOWrReq or IORdReq or DaWrConflict or DaRdConflict)
begin
    PAccess = (PrWrActive | PrRdActive);
    DWAccess = DaWrCycle & DaWrReq & ~DaWrConflict;
    DRAccess = DaRdCycle & DaRdReq & ~DaRdConflict;
    IWAccess = DaWrCycle & IOWrReq & ~DaWrConflict;
    IRAccess = DaRdCycle & IORdReq & ~DaRdConflict;
end

endmodule