m3s020ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Peripheral Block
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.105

// Revision history
// V1.005 - 27 June 1997
//          PMMRRdData tri-states removed.

// M320C50 Peripheral Block.
// Instantiates:
//    Memory-Mapped Register decode block
//    Wait-State generator
//    Timer
//    Serial Port
//    TDM Serial Port
//    Interrupt Generator


module m3s020ct (FClock, ClockCPU, Clock, Reset, WriteAddr, ReadAddr, MMRWriteData,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    PMMRRdData, PMMRWr, PMMRRd,
    DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr, READY, ERdy,
    CLKXI, CLKR, TCLKXI, TCLKR, DR, TDR, FSR, FSXI, TFSR, TFSXI,
    CLKXO, NCLKXE, TCLKXO, NTCLKXE, DWAccess, DRAccess, PAccess, IWAccess, IRAccess,
    DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE, TADD, NTADDE, TOUT,
    PerIntr);
    input         FClock, ClockCPU, Clock, Reset;
    input         PMMRWr, PMMRRd, READY;
    input         CLKXI, CLKR, TCLKXI, TCLKR;
    input         DR, TDR, FSR, FSXI, TFSR, TFSXI;
    input   [6:0] WriteAddr, ReadAddr;
    input  [15:0] MMRWriteData;
    input         DWAccess, DRAccess, PAccess, IWAccess, IRAccess;
    input   [2:0] DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo;
    input   [1:0] PAddr;
    output [15:0] PMMRRdData;
    output  [4:0] PerIntr;
    output        ERdy, CLKXO, NCLKXE, TCLKXO, NTCLKXE;
    output        DX, NDXE, TDX, NTDXE, FSXO, NFSXE, TFSXO, NTFSXE;
    output        TADD, NTADDE, TOUT;

    wire [15:0] PMMRRdData;
    wire  [3:0] SPIntr;
    wire  [4:0] PerIntr;
    wire  [5:0] SPRegCntrl;
    wire  [5:0] TimRegCntrl;
    wire  [5:0] WaitRegCntrl;
    wire [11:0] TDMRegCntrl;
    wire        TINT, RINT, XINT, TRNT, TXNT, TOUT;
    wire        ERdy;
    wire        DX, NDXE, FSXO, NFSXE;
    wire        TDX, NTDXE, TFSXO, NTFSXE, TADD, NTADDE;
    wire [15:0] WSGData, TimData, SPData, TSPData;


// Memory-mapped register decoder
m3s021ct U1 (WriteAddr, ReadAddr, PMMRWr, PMMRRd,
    WSGData, TimData, SPData, TSPData,
    SPRegCntrl, TimRegCntrl, WaitRegCntrl, TDMRegCntrl, PMMRRdData);

// Interrupt Generator
m3s022ct U2 (Reset, Clock, RINT, XINT, TRNT, TXNT, SPIntr);

// Wait-State Generator
m3s023ct U3 (FClock, ClockCPU, Reset, READY,
    DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr,
    DWAccess, DRAccess, PAccess, IWAccess, IRAccess, WaitRegCntrl, 
    MMRWriteData, ERdy, WSGData);

// Timer
m3s024ct U4 (Clock, Reset, TimRegCntrl, MMRWriteData,
    TINT, TOUT, TimData);

// Peripheral interrupts
assign PerIntr = {SPIntr,TINT};

// Serial Port
m3s025ct U5 (Clock, Reset, SPRegCntrl, MMRWriteData,
    CLKXI, CLKR, DX, NDXE, DR, FSXI, FSXO, NFSXE, FSR,
    CLKXO, NCLKXE, RINT, XINT, SPData);

// TDM Serial Port
m3s028ct U6 (Clock, Reset, TDMRegCntrl, MMRWriteData,
    TCLKXI, TCLKR, TDX, NTDXE, TDR, TFSXI, TFSXO, NTFSXE, TFSR, TADD, NTADDE,
    TCLKXO, NTCLKXE, TRNT, TXNT, TSPData);

endmodule