m3s007ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Central Arithmetic-Logic Unit
// Copyright Mentor Graphics Corporation and Licensors 1998
// V1.105

// m3s007ct
// M320C50 Central Arithmetic-Logic Unit top level.
// Instantiates the ALU/Accumulator block and the Multiplier.
// Provides:
//    Tempory registers TReg0, TReg1 & TReg2
//    ST0 bits 10-12
//    ST1 bits 0-3,5,6-11
//    Pre-scaler shift source selector
//    ProgBus/DataBus input selector
//
// MMRegCntrl:
//    0 : TReg0 MM reg write
//    1 : TReg1 MM reg write
//    2 : TReg2 MM reg write
//    3 : TReg0 MM reg read
//    4 : TReg1 MM reg read
//    5 : TReg2 MM reg read
//
// RegCntrl:
//    0 : TReg0 load
//    1 : PReg load
//    2 : PReg high load
//    3 : Acc load
//    4 : ST0 load
//    5 : ST1 load
//    6 : PReg low store
//    7 : PReg high store
//    8 : Acc store
//    9 : AccB load
//   10 : Clear ACC
//   11 : Clear PReg
//   12 : ST0 store
//   13 : ST1 store
//   14 : Load PM bits
//
// SelCntrl:
//    0 : Data source (0=Data, 1=Prog)
//    1 : Pre-scaler source is TReg1
//    2 : Pre-scaler source is TReg2
//    3 : Pre-scaler shift left 16
//    4 : Pre-scaler shift left 16 with rounding (ZALR)
//    5 : Suppress sign-extension
//  9:6 : CALU shift value and AR address
//
// ALUCntrl:
//  2:0 : ALU function control
//    3 : ALU source is ACCB
//    4 : ALU source is PReg
//    5 : ALU Carry input enable
//    6 : ALU NEG
//    7 : ALU ABS
//    8 : ALU SUBC
//    9 : ALU CRGT
//   10 : ALU CRLT
//   11 : ALU NORM
//
// SRCntrl:
//    0 : Enable shift/rotate
//    1 : Shift/rotate left (0=right, 1=left)
//    2 : Rotate (0=shift, 1=rotate)
//    3 : Include accumulator buffer
//    4 : BSAR instruction
//    5 : SATH instruction
//    6 : SATL instruction
//
// SetClrCntrl:
//    0 : Set/Clear value (1 = set, 0 = clear)
//    1 : OVM bit
//    2 : CNF bit
//    3 : SXM bit
//    4 : TC bit
//    5 : XF bit
//    6 : C bit
//    7 : HM bit
//
// TRM is the control bit for joining the T registers
// MPYU selects unsigned multiply
// PM is the P register output scaler control
// SXM and OVM are control flags in the status register controlling
//     sign extension and overflow mode
// ClrOV clears the OV flag
// BitTestEnab indicates a BIT or BITT instruction

module m3s007ct (ProgBus, DataBus, Clock, MemCycle, Reset,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  TRM, MMRegCntrl, RegCntrl, SelCntrl, ALUCntrl, SRCntrl, SetClrCntrl,
  ContextSave, ContextRestore, LdARTC, ARTC, PLUCmpr, PLUZero, MPYU,
  ClrOV, BitTestEnab, iMMR, DMAMode,
  AccNZ, AccLZ, TC, OV, C, NormEnab, NextCNF, XFFlag, NextHM,
  DataWrite, DataRead);

  input [15:0] ProgBus, DataBus;
  input [5:0] MMRegCntrl;
  input [14:0] RegCntrl;
  input [9:0] SelCntrl;
  input [11:0] ALUCntrl;
  input [6:0] SRCntrl;
  input [7:0] SetClrCntrl;
  input LdARTC, ARTC, PLUCmpr, PLUZero;
  input TRM;
  input BitTestEnab, iMMR, DMAMode;
  input MPYU;
  input ClrOV;
  input Clock, MemCycle, Reset;
  input ContextSave, ContextRestore;
  
  inout  [15:0] DataWrite;
  output [15:0] DataRead;
  output AccNZ, AccLZ, TC, OV, C;
  output NormEnab, NextCNF, XFFlag, NextHM;
  
  wire [31:0] MultOp;
  wire        AccNZ, AccLZ, C, OV, BitTest;
  
  reg [15:0] IpBus; // multiplexed data/program bus
  reg [15:0] TReg0, TReg0_C, NextTReg0, SourceTReg0;
  reg  [4:0] TReg1, TReg1_C, NextTReg1;
  reg  [3:0] TReg2, TReg2_C, NextTReg2;
  reg  [4:0] NextScalerShift, BarrelShift;
  reg  [3:0] PreScalerShift, PostScalerShift;
  reg  [2:0] ShiftCntrl;
  reg  [1:0] PM, PM_C, NextPM;
  reg        BusSelect, LastMemCycle;
  reg        SXM, OVM, CNF, XF, XFFlag, HM, TC, SXM_C, OVM_C, CNF_C, HM_C, TC_C;
  reg        NextSXM, NextOVM, NextCNF, NextXF, NextHM;
  reg        SourceTC1, SourceTC2, UpdateTC;
  wire       SourceTC, NextTC, NormEnab;


// MemCycle was valid last cycle
always @(posedge Clock)
    LastMemCycle <= MemCycle;

// TReg multiplexers
// TReg0 multiplexer split into 2 stages to exclude DataWrite from SourceTReg0
always @(MMRegCntrl or RegCntrl or iMMR or ContextRestore or LastMemCycle
     or TReg0 or TReg0_C or TReg1 or TReg1_C or TReg2 or TReg2_C
     or DataBus or DataWrite or TRM)
begin
    if (RegCntrl[0] | MMRegCntrl[0])
        SourceTReg0 = DataBus;
    else
        SourceTReg0 = TReg0;
    if (MMRegCntrl[0] & ~RegCntrl[0] & ~iMMR)
        NextTReg0 = DataWrite;
    else if (ContextRestore)
        NextTReg0 = TReg0_C;
    else
        NextTReg0 = SourceTReg0;
    if (((MMRegCntrl[1] & iMMR) | (RegCntrl[0] & ~TRM)) & LastMemCycle)
        NextTReg1 = DataBus[4:0];
    else if (MMRegCntrl[1] & ~iMMR & LastMemCycle)
        NextTReg1 = DataWrite[4:0];
    else if (ContextRestore & LastMemCycle)
        NextTReg1 = TReg1_C;
    else
        NextTReg1 = TReg1;
    if (((MMRegCntrl[2] & iMMR) | (RegCntrl[0] & ~TRM)) & LastMemCycle)
        NextTReg2 = DataBus[3:0];
    else if (MMRegCntrl[2] & ~iMMR & LastMemCycle)
        NextTReg2 = DataWrite[3:0];
    else if (ContextRestore & LastMemCycle)
        NextTReg2 = TReg2_C;
    else
        NextTReg2 = TReg2;
end

// Temporary registers
always @(posedge Clock)
begin
    if (LastMemCycle)
    begin
        TReg0 <= NextTReg0;
        TReg1 <= NextTReg1;
        TReg2 <= NextTReg2;
    end
    if (ContextSave)
    begin
        TReg0_C <= TReg0;
        TReg1_C <= TReg1;
        TReg2_C <= TReg2;
    end
end

// output control for T registers
assign DataRead = (MMRegCntrl[3]) ? NextTReg0[15:0] : 16'bZ;
assign DataRead = (MMRegCntrl[4]) ? {11'b0,NextTReg1[4:0]} : 16'bZ;
assign DataRead = (MMRegCntrl[5]) ? {12'b0,NextTReg2[3:0]} : 16'bZ;

// Mux for shift bus
always @(SelCntrl or NextTReg1 or NextTReg2)
begin
    NextScalerShift[4] = NextTReg1[4] & SelCntrl[1];
    case (SelCntrl[2:1])
        0: NextScalerShift[3:0] = SelCntrl[9:6];
        1: NextScalerShift[3:0] = NextTReg1[3:0];
        2: NextScalerShift[3:0] = NextTReg2[3:0];
        3: NextScalerShift[3:0] = NextTReg1[3:0];
    endcase
end

// Selection and shifter control latches
always @(posedge Clock)
if (MemCycle)
begin
    BusSelect <= SelCntrl[0];
    ShiftCntrl <= SelCntrl[5:3];
    PreScalerShift <= NextScalerShift[3:0];
    BarrelShift <= NextScalerShift;
    PostScalerShift <= NextScalerShift[3:0];
end
    
// PreScaler and multiplier input mux
always @(BusSelect or ProgBus or DataBus)
    if (BusSelect) IpBus = ProgBus;
    else IpBus = DataBus;

// Multiplier
// Input taken from SourceTReg0 to exclude DataWrite
m3s069ct U1 (MultOp, SourceTReg0, IpBus, MPYU);

// ALU and accumulator
m3s072ct U2 (DataBus, IpBus, MultOp, RegCntrl[11:0], ALUCntrl, SRCntrl,
  PM, ClrOV, SXM, OVM, SetClrCntrl[6], SetClrCntrl[0], LastMemCycle,
  PreScalerShift, BarrelShift, PostScalerShift, ShiftCntrl,
  ContextSave, ContextRestore, DMAMode, Clock, MemCycle, Reset,
  C, OV, AccNZ, AccLZ, NormEnab, BitTest, DataWrite);

// PM bits
always @(Reset or RegCntrl or ContextRestore
  or ProgBus or DataBus or PM_C or PM)
case ({RegCntrl[14],RegCntrl[5],ContextRestore,Reset})
    0: NextPM = PM;
    1: NextPM = 2'b00;
    2: NextPM = PM_C;
    3: NextPM = PM_C;
    4: NextPM = DataBus[1:0];
    5: NextPM = DataBus[1:0];
    6: NextPM = DataBus[1:0];
    7: NextPM = DataBus[1:0];
    default: NextPM = ProgBus[1:0];
endcase

// SXM
always @(Reset or RegCntrl or SetClrCntrl or ContextRestore
  or DataBus or SXM_C or SXM)
case ({RegCntrl[5],SetClrCntrl[3],ContextRestore,Reset})
    0: NextSXM = SXM;
    1: NextSXM = 1;
    2: NextSXM = SXM_C;
    3: NextSXM = SXM_C;
    4: NextSXM = SetClrCntrl[0];
    5: NextSXM = SetClrCntrl[0];
    6: NextSXM = SetClrCntrl[0];
    7: NextSXM = SetClrCntrl[0];
    default: NextSXM = DataBus[10];
endcase

// OVM
always @(RegCntrl or SetClrCntrl or ContextRestore
  or DataBus or OVM_C or OVM)
case ({RegCntrl[4],SetClrCntrl[1],ContextRestore})
    0: NextOVM = OVM;
    1: NextOVM = OVM_C;
    2: NextOVM = SetClrCntrl[0];
    3: NextOVM = SetClrCntrl[0];
    default: NextOVM = DataBus[11];
endcase

// CNF
always @(Reset or RegCntrl or SetClrCntrl or ContextRestore
  or DataBus or CNF_C or CNF)
case ({RegCntrl[5],SetClrCntrl[2],ContextRestore,Reset})
    0: NextCNF = CNF;
    1: NextCNF = 0;
    2: NextCNF = CNF_C;
    3: NextCNF = CNF_C;
    4: NextCNF = SetClrCntrl[0];
    5: NextCNF = SetClrCntrl[0];
    6: NextCNF = SetClrCntrl[0];
    7: NextCNF = SetClrCntrl[0];
    default: NextCNF = DataBus[12];
endcase

// XF
always @(Reset or RegCntrl or SetClrCntrl or DataBus or XF)
case ({RegCntrl[5],SetClrCntrl[5],Reset})
    0: NextXF = XF;
    1: NextXF = 1;
    2: NextXF = SetClrCntrl[0];
    3: NextXF = SetClrCntrl[0];
    default: NextXF = DataBus[4];
endcase

// HM
always @(Reset or RegCntrl or SetClrCntrl or ContextRestore
  or DataBus or HM_C or HM)
case ({RegCntrl[5],SetClrCntrl[7],ContextRestore,Reset})
    0: NextHM = HM;
    1: NextHM = 1;
    2: NextHM = HM_C;
    3: NextHM = HM_C;
    4: NextHM = SetClrCntrl[0];
    5: NextHM = SetClrCntrl[0];
    6: NextHM = SetClrCntrl[0];
    7: NextHM = SetClrCntrl[0];
    default: NextHM = DataBus[6];
endcase

// TC bit
always @(RegCntrl or SetClrCntrl or BitTestEnab or PLUCmpr
  or LdARTC or ALUCntrl or ContextRestore or LastMemCycle
  or DataBus or BitTest or PLUZero or ARTC or NormEnab or TC_C or TC)
begin
    UpdateTC = BitTestEnab | PLUCmpr | LdARTC | (ALUCntrl[11] & LastMemCycle);
    case ({BitTestEnab,PLUCmpr,LdARTC})
        0: SourceTC1 = ~NormEnab;
        1: SourceTC1 = ARTC;
        2: SourceTC1 = PLUZero;
        3: SourceTC1 = PLUZero;
        default: SourceTC1 = BitTest;
    endcase
    case ({RegCntrl[5],SetClrCntrl[4],ContextRestore})
        0: SourceTC2 = TC;
        1: SourceTC2 = TC_C;
        2: SourceTC2 = SetClrCntrl[0];
        3: SourceTC2 = SetClrCntrl[0];
        default: SourceTC2 = DataBus[11];
    endcase
end

// TC update control
m3s047ct U3 (UpdateTC, MemCycle, SourceTC1, SourceTC2, TC, SourceTC, NextTC);

always @(posedge Clock)
begin
    PM <= NextPM;
    SXM <= NextSXM;
    OVM <= NextOVM;
    CNF <= NextCNF;
    XF <= NextXF;
    HM <= NextHM;
    TC <= NextTC;
end

// context save values
always @(posedge Clock)
    if (ContextSave)
    begin
        SXM_C <= SXM;
        OVM_C <= OVM;
        CNF_C <= CNF;
        TC_C <= TC;
        HM_C <= HM;
        PM_C <= NextPM;
    end

// status register outputs
assign DataWrite[12:10] = (RegCntrl[12] & ~DMAMode) ? {OV,NextOVM,1'b1} : 3'bZ;
assign DataWrite[12:0] = (RegCntrl[13] & ~DMAMode) ?
     {NextCNF,SourceTC,NextSXM,C,2'b11,NextHM,1'b1,NextXF,2'b11,NextPM} : 13'bZ;

// XF flag synchronisation, note timing is different if altered by LST1 instruction
always @(negedge Clock)
    if (RegCntrl[5])
        XFFlag <= NextXF;
    else
        XFFlag <= XF;

endmodule