m3s073ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// 32-bit (4-bit slice) Fast Look-Ahead ALU
// Copyright Mentor Graphics Corporation and Licensors 1998.

// m3s073ct
// M320C50 32-bit (4 bit slice) Fast Look-Ahead ALU

module m3s073ct (ALU_Op, A, B, CarryIn, CarryOut, OV, ALUFunction, ABSOL, NEG, LdCOV);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //

  input [31:0] A, B;
  input        CarryIn, ABSOL, NEG;
  input  [2:0] ALUFunction;
  
  output [31:0] ALU_Op;
  output CarryOut; // Carry output
  output OV;       // Overflow output
  output LdCOV;    // Update C and OV flags

  reg  [31:0] NA, NB;
  reg   [7:0] CarrySlice;
  reg         NCarryIn;

  wire  [7:0] NCarrySlice;
  wire [31:0] PartialSum, PartialCarry; // partial(bitwise) sums and carrys
  reg NG_30, NP_30 ; // generate propagate signals for overflow output

  reg [5:0] ALU_CntrlBit; // bitwise ALU control bits
  reg [7:0] NG, NP; // propagate generate carry signals for bit slices
  reg       LdCOV, OV;
  
  integer i;
  
// The only way to implement this design is hierarchically
// or synthesisers will destroy its speed

always @(A) NA = ~A;
always @(B) NB = ~B;

// decode ALU control
always @(ALUFunction)
case (ALUFunction)
    0: ALU_CntrlBit = 6'b000000; // ALU out = 0
    1: ALU_CntrlBit = 6'b000011; // ALU out = not A
    2: ALU_CntrlBit = 6'b001110; // ALU out = A or B
    3: ALU_CntrlBit = 6'b001010; // ALU out = A xor B
    4: ALU_CntrlBit = 6'b011010; // ALU out = A + B
    5: ALU_CntrlBit = 6'b000100; // ALU out = A and B
    6: ALU_CntrlBit = 6'b100101; // ALU out = A - B
    7: ALU_CntrlBit = 6'b000110; // ALU out = B
endcase

// decode LdCOV from ALUFunction
always @(ALUFunction or NEG or ABSOL)
    if ((ALUFunction == 4) | (ALUFunction == 6) | NEG | ABSOL)
        LdCOV = 1;
    else
        LdCOV = 0;

// generate partial sum carrys
m3s074ct U1(A, NA, B, NB, ALU_CntrlBit, PartialSum, PartialCarry);

// generate propagate and generate carry signals for bit slices
always @(PartialSum or PartialCarry)
begin
  for (i=0;i<8;i=i+1)
  begin
    NG[i] = (!(PartialCarry[i*4] & PartialSum[(i*4) + 1] & PartialSum[(i*4) + 2] & PartialSum[(i*4) + 3]) &
             !(PartialCarry[(i*4) + 1] & PartialSum[(i*4) + 2] & PartialSum[(i*4) + 3]) &
	     !(PartialCarry[(i*4) + 2] & PartialSum[(i*4) + 3]) &
	     !(PartialCarry[(i*4) + 3]));
    NP[i] = !(PartialSum[(i*4)] & PartialSum[(i*4) + 1] & PartialSum[(i*4) + 2] & PartialSum[(i*4) + 3]);
  end
end

// generate slice carrys
m3s075ct U2(NG, NP, NCarryIn, NCarrySlice);

// get inverses of carrys
always @(NCarrySlice) CarrySlice = ~NCarrySlice;
always @(CarryIn) NCarryIn = ~CarryIn;

// finally get result (slice at a time)
m3s076ct U3(PartialSum[3:0], PartialCarry[2:0], CarryIn, ALU_Op[3:0]);
m3s076ct U4(PartialSum[7:4], PartialCarry[6:4], CarrySlice[0], ALU_Op[7:4]);
m3s076ct U5(PartialSum[11:8], PartialCarry[10:8], CarrySlice[1], ALU_Op[11:8]);
m3s076ct U6(PartialSum[15:12], PartialCarry[14:12], CarrySlice[2], ALU_Op[15:12]);
m3s076ct U7(PartialSum[19:16], PartialCarry[18:16], CarrySlice[3], ALU_Op[19:16]);
m3s076ct U8(PartialSum[23:20], PartialCarry[22:20], CarrySlice[4], ALU_Op[23:20]);
m3s076ct U9(PartialSum[27:24], PartialCarry[26:24], CarrySlice[5], ALU_Op[27:24]);
m3s076ct U10(PartialSum[31:28], PartialCarry[30:28], CarrySlice[6], ALU_Op[31:28]);

// carry output = top slice!
assign CarryOut = CarrySlice[7];

// Overflow output = carry from bit 30 modified by carry output and bit 31
always @(PartialCarry or PartialSum or NCarrySlice or CarrySlice)
begin
    NG_30 = (~(PartialCarry[28] & PartialSum[29] & PartialSum[30]) &
                ~(PartialCarry[29] & PartialSum[30]) &
		~PartialCarry[30]);
    NP_30 = ~(PartialSum[28] & PartialSum[29] & PartialSum[30]);
    OV = ~((((NCarrySlice[6] & NG_30) | (NG_30 & NP_30)) ^ CarrySlice[7]) | PartialSum[31]);
end	

endmodule