m3s011ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Dual-port Memory Controller
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.101

// Revision history
// V1.101 - 20 November 1996
//          Writes delayed by one cycle.
//          Data reads extended until end of memory cycle.
// V1.100 - 22 October 1996
//          PACntrl14 delayed by one cycle.

// m3s011ct
// M320C50 internal dual-port memory controller.
// Provides address and control signals for the internal dual-port memory.
// Cycle goes high during the first cycle of each pipeline advance and enable
// the read and write strobes.
// Read and write strobes go low during the 2nd half of an active cycle.

module m3s011ct (ProgAddr, WriteAddr, ReadAddr, CNF,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    PrWrReq, PrRdReq, DaWrReq, DaRdReq,
    MemCycle, FClock, Clock, Reset, MemAccEnab, PACntrl14,
    WriteReady, B0WA, B0RA, WA, RA, NBWR, NBRD,
    DpDataValid, DpProgValid, DpRdWrDet);

    input  [8:0] ProgAddr, WriteAddr, ReadAddr;
    input        CNF, PrWrReq, PrRdReq, MemCycle, FClock, Clock, Reset;
    input        WriteReady, MemAccEnab, PACntrl14;
    input  [2:0] DaWrReq, DaRdReq;
    output [8:0] B0WA, B0RA, WA, RA;
    output [2:0] NBWR, NBRD;
    output       DpDataValid, DpProgValid, DpRdWrDet;

    reg [8:0] B0WA, B0RA, WA, RA;
    reg [2:0] NBWR, NBRD;
    reg       Cycle, DpDataValid, DpProgValid, PACntrl14Del;
    reg       DpRdWrDet, AddrCmp, PrWrReqDel, CNFDel;
    reg [2:0] DaWrReqDel;

// Post write address and write requests
always @(posedge Clock)
if (MemCycle)
begin
    if (CNF)
        B0WA <= ProgAddr;
    else
        B0WA <= WriteAddr;
    WA <= WriteAddr;
    PrWrReqDel <= PrWrReq;
    DaWrReqDel <= DaWrReq;
    CNFDel <= CNF;
end

// Read address
always @(ProgAddr or ReadAddr or CNF)
begin
    if (CNF)
        B0RA = ProgAddr;
    else
        B0RA = ReadAddr;
    RA = ReadAddr;
end

// Cycle controller
always @(posedge Clock or posedge Reset)
    if (Reset)
        Cycle <= 0;
    else
        Cycle <= MemCycle;

// Read strobe
always @(posedge FClock or posedge Reset)
    if (Reset)
        NBRD[2:0] <= 3'b111;
    else if (Clock)
    begin
        if (CNF) NBRD[0] <= ~(PrRdReq & MemAccEnab);
        else NBRD[0] <= ~(DaRdReq[0] & MemAccEnab);
        NBRD[1] <= ~(DaRdReq[1] & MemAccEnab);
        NBRD[2] <= ~(DaRdReq[2] & MemAccEnab);
    end
    else
        NBRD[2:0] <= 3'b111;

// write strobe
always @(posedge FClock or posedge Reset)
    if (Reset)
        NBWR[2:0] <= 3'b111;
    else if (Cycle & Clock)
    begin
        if (CNFDel) NBWR[0] <= ~(PrWrReqDel & MemAccEnab);
        else NBWR[0] <= ~(DaWrReqDel[0] & MemAccEnab);
        NBWR[1] <= ~(DaWrReqDel[1] & MemAccEnab);
        NBWR[2] <= ~(DaWrReqDel[2] & MemAccEnab);
    end
    else
        NBWR[2:0] <= 3'b111;

// Read data valid signal
always @(WriteReady or DaRdReq or Cycle)
    DpDataValid = WriteReady & (DaRdReq[0] | DaRdReq[1] | DaRdReq[2]);

// Delay PACntrl14
always @(posedge Clock)
   if (MemCycle)
      PACntrl14Del <= PACntrl14;

// Read program valid signal
always @(PrRdReq or Cycle or WriteReady or PACntrl14Del)
    DpProgValid = PrRdReq & Cycle & (WriteReady | ~PACntrl14Del);

// Compare read and write addresses
always @(WriteAddr or ReadAddr)
    if (WriteAddr == ReadAddr)
        AddrCmp = 1;
    else
        AddrCmp = 0;

// Check for read of dirty location
always @(DaWrReq or DaRdReq or AddrCmp)
    DpRdWrDet = ((DaRdReq[0] & DaWrReq[0]) |
                 (DaRdReq[1] & DaWrReq[1]) |
                 (DaRdReq[2] & DaWrReq[2])) & AddrCmp;

endmodule