m3s015ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Memory-Mapped Registers
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.104

// Revision history
// V1.104 - 27 June 1997
//          Number of tri-state drivers reduced.
// V1.103 - 18 November 1996
//          Clearing of BRAF by PMST write delayed.
//          PMMRWriteData latch removed.

// m3s015ct
// M320C50 Memory mapped registers.
// Decodes all core memory mapped registers and implements:
//     GREG and PMST.
// PMST has a synchronous reset and the MPNMC bit is reset to the value of the MPNMC input.
// Latches data from peripheral memory-mapped registers, adding a wait state
// to peripheral memory-mapped register read cycles.
//
// Control outputs:
//    IntRegCntrl: 0) IMR write,  1) IFR write,  2) IMR read,  3) IFR read.
//    RptRegCntrl: 0) RPTC write,  1) RPTC read.
//   BrptRegCntrl: 0) BRCR write,  1) PASR write,  2) PAER write,
//                 3) BRCR read,   4) PASR read,   5) PAER read.
//   DBMRRegCntrl: 0) DBMR read,  1) DBMR write.
//    AuxRegCntrl: 0) AR write,  1) INDX write,  2) ARCR write,
//                 3) CBSR1 write, 4) CBER1 write,
//                 5) CBSR2 write, 6) CBER2 write, 7) CBCR write,
//                 8) AR read,   9) INDX read,   10) ARCR read,
//                 11) CBSR1 read, 11) CBER1 read,
//                 13) CBSR2 read, 14) CBER2 read, 15) CBCR read.
//      TRegCntrl: 0) TREG0 write,  1) TREG1 write,  2) TREG2 write,
//                 3) TREG0 read,   4) TREG1 read,   5) TREG2 read.
//   BMARRegCntrl: 0) BMAR write,  1) BMAR read.
//

module m3s015ct (DataBus, WriteAddr, ReadAddr, FClock, Clock, Reset, AdvPipe, MemCycle,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    MPNMC, MMWrRq, MMRdRq, ContextSave, ContextRestore,
    SetBRAF, ClrBRAF, iMMR, RptOut, PMMRRdData,
    MPNMCreg, RAMreg, OVLYreg, IPTR, TRMreg, BRAFreg, NDXreg, AVISreg, GAddrEnab,
    IntRegCntrl, RptRegCntrl, BrptRegCntrl, DBMRRegCntrl, AuxRegCntrl, TRegCntrl,
    BMARRegCntrl, MMDataValid, MMRReady, PMMRWrS, PMMRRd, WriteReady,
    PMMRWrAddr, PMMRRdAddr, MMRWriteData, DataWrite, DataRead);

    input [15:0] DataBus, PMMRRdData, DataWrite;
    input  [6:0] WriteAddr, ReadAddr;
    input        FClock, Clock, Reset, AdvPipe, MemCycle, MMWrRq, MMRdRq, MPNMC, WriteReady;
    input        ContextSave, ContextRestore, SetBRAF, ClrBRAF, iMMR, RptOut;
    output [7:0] GAddrEnab;
    output [3:0] IntRegCntrl;
    output [1:0] RptRegCntrl;
    output [5:0] BrptRegCntrl;
    output [1:0] DBMRRegCntrl, BMARRegCntrl;
    output [15:0] AuxRegCntrl;
    output [5:0] TRegCntrl;
    output [15:0] DataRead, MMRWriteData;
    output       MPNMCreg, RAMreg, OVLYreg, TRMreg, BRAFreg, NDXreg, AVISreg;
    output       MMRReady, PMMRWrS, PMMRRd, MMDataValid;
    output [6:0] PMMRWrAddr, PMMRRdAddr;
    output [4:0] IPTR;

    reg  [7:0] GREG, NextGREG, GAddrEnab;
    reg  [4:0] IPTR, IPTR_C, NextIPTR;
    reg        BRAFreg, BRAFreg_C, TRMreg, TRMreg_C, NDXreg, NDXreg_C, MPNMCreg, MPNMCreg_C;
    reg        RAMreg, RAMreg_C, OVLYreg, OVLYreg_C, AVISreg, AVISreg_C, PMST6, PMST6_C;
    reg        NextBRAF, NextTRM, NextNDX, NextMPNMC, NextRAM, NextOVLY, NextAVIS, NextPMST6;
    reg  [2:0] PMST8, PMST8_C, NextPMST8;
    reg  [3:0] IntRegCntrl;
    reg  [1:0] RptRegCntrl;
    reg  [5:0] BrptRegCntrl;
    reg  [1:0] DBMRRegCntrl, BMARRegCntrl;
    reg [15:0] AuxRegCntrl;
    reg  [5:0] TRegCntrl;
    reg  [6:0] PMMRWrAddr, PMMRRdAddr;
    reg        WriteGREG, ReadGREG, WritePMST, ReadPMST, MMDataValid;
    reg        PMMRRdDec, PMMRWrDec, PMMRRdCycle, PMMRWrCycle;
    reg        MMRReady, PMMRWr, PMMRRd, ResetNeg, PMMRWrS;
    reg        PMSTClrBRAF, AllClrBRAF, DataReadEnab;
    reg [15:0] PMMRRdDataReg, MMRWriteData, NextPMMRRdData, DataReadOp;


// Read/write control decode task
task Decode;
    input [6:0] Addr;
    input [6:0] WriteAddr;
    input [6:0] ReadAddr;
    input       MMWrRq;
    input       MMRdRq;
    output      WriteCntrl;
    output      ReadCntrl;
begin
    if ((WriteAddr == Addr) & MMWrRq) WriteCntrl = 1;
    else WriteCntrl = 0;
    if ((ReadAddr == Addr) & MMRdRq) ReadCntrl = 1;
    else ReadCntrl = 0;
end
endtask


// Address decode
always @(WriteAddr or ReadAddr or MMWrRq or MMRdRq
// Compass synthesizer requires task outputs to be declared in the sensitivity list
or IntRegCntrl or WriteGREG or ReadGREG or WritePMST or ReadPMST or RptRegCntrl
or BrptRegCntrl or TRegCntrl or DBMRRegCntrl or AuxRegCntrl or BMARRegCntrl)
begin
    Decode (7'h04, WriteAddr, ReadAddr, MMWrRq, MMRdRq, IntRegCntrl[0], IntRegCntrl[2]);
    Decode (7'h05, WriteAddr, ReadAddr, MMWrRq, MMRdRq, WriteGREG, ReadGREG);
    Decode (7'h06, WriteAddr, ReadAddr, MMWrRq, MMRdRq, IntRegCntrl[1], IntRegCntrl[3]);
    Decode (7'h07, WriteAddr, ReadAddr, MMWrRq, MMRdRq, WritePMST, ReadPMST);
    Decode (7'h08, WriteAddr, ReadAddr, MMWrRq, MMRdRq, RptRegCntrl[0], RptRegCntrl[1]);
    Decode (7'h09, WriteAddr, ReadAddr, MMWrRq, MMRdRq, BrptRegCntrl[0], BrptRegCntrl[3]);
    Decode (7'h0A, WriteAddr, ReadAddr, MMWrRq, MMRdRq, BrptRegCntrl[1], BrptRegCntrl[4]);
    Decode (7'h0B, WriteAddr, ReadAddr, MMWrRq, MMRdRq, BrptRegCntrl[2], BrptRegCntrl[5]);
    Decode (7'h0C, WriteAddr, ReadAddr, MMWrRq, MMRdRq, TRegCntrl[0], TRegCntrl[3]);
    Decode (7'h0D, WriteAddr, ReadAddr, MMWrRq, MMRdRq, TRegCntrl[1], TRegCntrl[4]);
    Decode (7'h0E, WriteAddr, ReadAddr, MMWrRq, MMRdRq, TRegCntrl[2], TRegCntrl[5]);
    Decode (7'h0F, WriteAddr, ReadAddr, MMWrRq, MMRdRq, DBMRRegCntrl[1], DBMRRegCntrl[0]);
    Decode (7'h18, WriteAddr, ReadAddr, MMWrRq, MMRdRq, AuxRegCntrl[1], AuxRegCntrl[9]);
    Decode (7'h19, WriteAddr, ReadAddr, MMWrRq, MMRdRq, AuxRegCntrl[2], AuxRegCntrl[10]);
    Decode (7'h1A, WriteAddr, ReadAddr, MMWrRq, MMRdRq, AuxRegCntrl[3], AuxRegCntrl[11]);
    Decode (7'h1B, WriteAddr, ReadAddr, MMWrRq, MMRdRq, AuxRegCntrl[4], AuxRegCntrl[12]);
    Decode (7'h1C, WriteAddr, ReadAddr, MMWrRq, MMRdRq, AuxRegCntrl[5], AuxRegCntrl[13]);
    Decode (7'h1D, WriteAddr, ReadAddr, MMWrRq, MMRdRq, AuxRegCntrl[6], AuxRegCntrl[14]);
    Decode (7'h1E, WriteAddr, ReadAddr, MMWrRq, MMRdRq, AuxRegCntrl[7], AuxRegCntrl[15]);
    Decode (7'h1F, WriteAddr, ReadAddr, MMWrRq, MMRdRq, BMARRegCntrl[0], BMARRegCntrl[1]);
    if ((WriteAddr[6:3] == 4'b0010) & MMWrRq) AuxRegCntrl[0] = 1;
    else AuxRegCntrl[0] = 0;
    if ((ReadAddr[6:3] == 4'b0010) & MMRdRq) AuxRegCntrl[8] = 1;
    else AuxRegCntrl[8] = 0;
end

// Data valid signal
always @(MMRdRq or WriteReady)
    MMDataValid = MMRdRq & WriteReady;

// MMR write data multiplexer
always @(iMMR or DataBus or DataWrite)
    if (iMMR)
        MMRWriteData = DataBus;
    else
        MMRWriteData = DataWrite;

// Clearing of BRAF by write to PMST
always @(posedge Clock)
    PMSTClrBRAF <= WritePMST & ~MMRWriteData[0];

always @(ClrBRAF or PMSTClrBRAF)
    AllClrBRAF = ClrBRAF | PMSTClrBRAF;

// PMST
always @(Reset or WritePMST or iMMR or ContextRestore or SetBRAF or AllClrBRAF
      or MMRWriteData or BRAFreg or TRMreg or NDXreg or MPNMC
      or MPNMCreg or RAMreg or OVLYreg or AVISreg or IPTR or BRAFreg_C or TRMreg_C
      or NDXreg_C or MPNMCreg_C or RAMreg_C or OVLYreg_C or AVISreg_C or IPTR_C
      or PMST6 or PMST6_C or PMST8 or PMST8_C)
    if (Reset)
    begin
        NextBRAF = 0;
        NextTRM = 0;
        NextNDX = 0;
        NextMPNMC = MPNMC;
        NextRAM = 0;
        NextOVLY = 0;
        NextPMST6 = 0;
        NextAVIS = 0;
        NextPMST8 = 0;
        NextIPTR = 0;
    end
    else if (WritePMST)
    begin
        NextBRAF = BRAFreg;
        NextTRM = MMRWriteData[1];
        NextNDX = MMRWriteData[2];
        NextMPNMC = MMRWriteData[3];
        NextRAM = MMRWriteData[4];
        NextOVLY = MMRWriteData[5];
        NextPMST6 = MMRWriteData[6];
        NextAVIS = MMRWriteData[7];
        NextPMST8 = MMRWriteData[10:8];
        NextIPTR = MMRWriteData[15:11];
    end
    else if (ContextRestore)
    begin
        NextBRAF = BRAFreg_C;
        NextTRM = TRMreg_C;
        NextNDX = NDXreg_C;
        NextMPNMC = MPNMCreg_C;
        NextRAM = RAMreg_C;
        NextOVLY = OVLYreg_C;
        NextPMST6 = PMST6_C;
        NextAVIS = AVISreg_C;
        NextPMST8 = PMST8_C;
        NextIPTR = IPTR_C;
    end
    else
    begin
        if (SetBRAF) NextBRAF = 1;
        else if (AllClrBRAF) NextBRAF = 0;
        else NextBRAF = BRAFreg;
        NextTRM = TRMreg;
        NextNDX = NDXreg;
        NextMPNMC = MPNMCreg;
        NextRAM = RAMreg;
        NextOVLY = OVLYreg;
        NextPMST6 = PMST6;
        NextAVIS = AVISreg;
        NextPMST8 = PMST8;
        NextIPTR = IPTR;
    end

always @(posedge Clock)
begin
    if (AdvPipe | Reset)
    begin
        BRAFreg <= NextBRAF;
        TRMreg <= NextTRM;
        NDXreg <= NextNDX;
        MPNMCreg <= NextMPNMC;
        RAMreg <= NextRAM;
        OVLYreg <= NextOVLY;
        PMST6 <= NextPMST6;
        AVISreg <= NextAVIS;
        PMST8 <= NextPMST8;
        IPTR <= NextIPTR;
    end
    if (ContextSave)
    begin
        BRAFreg_C <= BRAFreg;
        TRMreg_C <= TRMreg;
        NDXreg_C <= NDXreg;
        MPNMCreg_C <= MPNMCreg;
        RAMreg_C <= RAMreg;
        OVLYreg_C <= OVLYreg;
        PMST6_C = NextPMST6;
        AVISreg_C <= AVISreg;
        PMST8_C = NextPMST8;
        IPTR_C <= IPTR;
    end
end

// GREG
always @(Reset or WriteGREG or iMMR or GREG or MMRWriteData)
    if (Reset) NextGREG = 8'b0;
    else if (WriteGREG) NextGREG = MMRWriteData[7:0];
    else NextGREG = GREG;
always @(posedge Clock)
    GREG <= NextGREG;

// Global address enable
always @(GREG)
    if (GREG[7:2])
        GAddrEnab = GREG;
    else
        GAddrEnab = 0;

// Peripheral address decode
always @(MMWrRq or MMRdRq or WriteAddr or ReadAddr
     or PMMRRdCycle or PMMRWrCycle or RptOut)
begin
    PMMRWrDec = MMWrRq & (WriteAddr[6] | WriteAddr[5]);
    PMMRRdDec = MMRdRq & (ReadAddr[6] | ReadAddr[5]);
    PMMRRd = PMMRRdDec & ~PMMRRdCycle;
    PMMRWr = PMMRWrDec & ~PMMRWrCycle;
    MMRReady = ~(PMMRWr | (PMMRRd & ~RptOut));	// No wait state for OUT instruction
end

// Reset synchronised to positive edge of clock
always @(posedge Clock)
    ResetNeg <= Reset;

// PMMR write address latch
always @(posedge FClock)
if (Clock)
    PMMRWrAddr <= WriteAddr;
always @(ReadAddr)
    PMMRRdAddr = ReadAddr;

// PMMR write strobe
always @(posedge FClock or posedge ResetNeg)
    if (ResetNeg)
        PMMRWrS <= 0;
    else if (Clock)
        PMMRWrS <= PMMRWr;

// Peripheral read data latch
always @(PMMRRd or PMMRRdData or PMMRRdDataReg)
    if (PMMRRd)
        NextPMMRRdData = PMMRRdData;
    else
        NextPMMRRdData = PMMRRdDataReg;
always @(posedge Clock)
    PMMRRdDataReg <= NextPMMRRdData;

// Peripheral wait state generator
always @(posedge Clock)
    if (Reset)
    begin
        PMMRRdCycle <= 0;
        PMMRWrCycle <= 0;
    end
    else
    begin
        if (PMMRRdDec & ~PMMRRdCycle) PMMRRdCycle <= 1;
        if (MemCycle & PMMRRdCycle) PMMRRdCycle <= 0;
        if (PMMRWrDec & ~PMMRWrCycle) PMMRWrCycle <= 1;
        if (MemCycle & PMMRWrCycle) PMMRWrCycle <= 0;
    end

// DataRead output mux
always @(ReadGREG or ReadPMST or PMMRRdDec or NextGREG or
    NextIPTR or NextPMST8 or NextAVIS or NextPMST6 or NextOVLY or
    NextRAM or NextMPNMC or NextNDX or NextTRM or NextBRAF or NextPMMRRdData)
begin
    if (ReadGREG) DataReadOp = {8'hFF,NextGREG};
    else if (ReadPMST) DataReadOp = {NextIPTR,NextPMST8,NextAVIS,NextPMST6,
            NextOVLY,NextRAM,NextMPNMC,NextNDX,NextTRM,NextBRAF};
    else DataReadOp = NextPMMRRdData;
    DataReadEnab = ReadGREG | ReadPMST | PMMRRdDec;
end

// Output tri-states
assign DataRead = DataReadEnab ? DataReadOp : 16'bZ;

endmodule