📄 m3s027ct.v
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//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra //// Serial Port Receiver// Copyright Mentor Graphics Corporation and Licensors 1998. // V1.005// m3s027ct// M320C50 Serial port receiver.// DR is the input data// FSXI and FSXO are the Frame Synchronisation signals for receive operation.// FO, FSM are control signals from the SPC register.// RxSRFull is the receive shift register overflow signal// RxRdy is the receive ready flag// RINT is the receive interrupt// State machine definitions`define C_DRR_EMPTY_RSR_EMPTY 0`define C_DRR_FULL_RSR_EMPTY 1`define C_DRR_EMPTY_RSR_FULL 2`define C_DRR_FULL_RSR_FULL 3module m3s027ct (Clock, RxClock, NRxClock, RxReset, MMRWriteData, WriteDRR, ReadDRR,//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra // DR, FSR, FO, FSM, RxSRFull, RxRdy, NextDRR, RINT); input [15:0] MMRWriteData; input Clock, RxClock, NRxClock, RxReset, WriteDRR, ReadDRR; input DR, FSR, FO, FSM; output [15:0] NextDRR; output RxSRFull, RINT, RxRdy; reg [15:0] DRR, NextDRR, RSR; reg RxSRFull, SetSRFullFlag, SetSRFull1, SetSRFull2; reg [3:0] RxCount; // receive bit counter reg RINT, RxRdy, RxRdyReg, ClrRxRdy; reg RdDRRSync, RdDRRTemp; // DRR read strobe sync latches reg LdDRRSync, LdDRR1, LdDRR2; // DRR load strobe sync latches reg FSRSync, ReceivingFrame, NextReceivingFrame; reg [1:0] RxState; reg LastBit, LoadDRR;// // DRR register//always @(MMRWriteData or WriteDRR or LdDRRSync or RSR or DRR)begin if (WriteDRR) NextDRR = MMRWriteData; else if (LdDRRSync) NextDRR = RSR; else NextDRR = DRR;endalways @(posedge Clock)begin DRR <= NextDRR;end// Latch ReadDRR until RdDRRSync has gone highalways @(posedge Clock) RdDRRTemp <= (ReadDRR | (RdDRRTemp & ~RdDRRSync)) & RxReset;// Generate RdDRRSync signal, synchronised to RxClockalways @(posedge RxClock or negedge RxReset)begin if (~RxReset) RdDRRSync <= 0; else RdDRRSync <= RdDRRTemp;end//// receive control state machine//always @(posedge NRxClock or negedge RxReset) // negedge because RxRdy changes on thisbegin if (~RxReset) RxState <= `C_DRR_EMPTY_RSR_EMPTY; // reset state else case (RxState) `C_DRR_EMPTY_RSR_EMPTY: // can only go one place from here if (LastBit) RxState <= `C_DRR_EMPTY_RSR_FULL; // frame fills RSR `C_DRR_FULL_RSR_EMPTY: if (LastBit && !RdDRRSync) RxState <= `C_DRR_FULL_RSR_FULL; // about to overrun else if (LastBit & RdDRRSync) RxState <= `C_DRR_EMPTY_RSR_FULL; // read just in time! else if (RdDRRSync) // read in advance RxState <= `C_DRR_EMPTY_RSR_EMPTY; `C_DRR_EMPTY_RSR_FULL: // always fill DRR in this case RxState <= `C_DRR_FULL_RSR_EMPTY; `C_DRR_FULL_RSR_FULL: // either get a read or overrun if (RdDRRSync) RxState <= `C_DRR_EMPTY_RSR_FULL; default: // there isn't one but for safety RxState <= RxState; endcaseend//// LastBit signal//always @(RxCount or ReceivingFrame)begin LastBit = ((RxCount == 15) && ReceivingFrame);end// Generate SetSRFullFLag, synchronised to -ve edge of RXClockalways @(posedge NRxClock or negedge RxReset) if (~RxReset) SetSRFullFlag <= 0; else SetSRFullFlag <= (RxState == `C_DRR_FULL_RSR_FULL) && (~FSM | FSR);// RxSRFull flag re-synchronised to Clockalways @(posedge Clock or negedge RxReset) if (~RxReset) begin SetSRFull1 <= 0; SetSRFull2 <= 0; RxSRFull <= 0; end else begin SetSRFull1 <= SetSRFullFlag; SetSRFull2 <= SetSRFull1; RxSRFull <= ((SetSRFull1 & ~SetSRFull2) | RxSRFull) & ~ReadDRR; end// Receive counter - counts 0,1,2...6,15 if FO == 1, 0 to 15 if FO == 0//always @(posedge NRxClock or negedge RxReset)begin if (!RxReset) // asynchronous set RxCount <= 4'b1111 ; // note below that RxSRFull will abort the receive else if (FSRSync && !RxSRFull) // synchronous reset of counter RxCount <= 4'b0 ; else if (FO && (RxCount == 6)) // FO controls 8/16 bit operation RxCount <= 15; else RxCount <= RxCount + 1;end//// Receiving frame flag//always @(RxReset or FSRSync or RxSRFull or LastBit or FSM or RxState or ReceivingFrame)begin if (~RxReset) NextReceivingFrame = 0; else if (FSRSync & ~RxSRFull) NextReceivingFrame = 1; else if (LastBit & (FSM | (RxSRFull && (RxState == `C_DRR_FULL_RSR_FULL)))) NextReceivingFrame = 0; else NextReceivingFrame = ReceivingFrame;endalways @(posedge NRxClock or negedge RxReset)begin if (~RxReset) ReceivingFrame <= 0; else ReceivingFrame <= NextReceivingFrame;end// // Frame Sync control synchronisation//always @(posedge NRxClock or negedge RxReset)begin if (~RxReset) FSRSync <= 0; else FSRSync <= FSR;end//// RSR = receive shift register//always @(posedge NRxClock)begin if (NextReceivingFrame) RSR <= {RSR[14:0],DR};end//// generate LoadDRR signal//always @(LastBit)begin LoadDRR = LastBit;end//// sychronise load signal to Clock//always @(posedge Clock)begin LdDRR1 <= LoadDRR; LdDRR2 <= LdDRR1;endalways @(LdDRR1 or LdDRR2)begin LdDRRSync = LdDRR1 & ~LdDRR2;end//// Generate RxRdy clear signal from ReadDRR//always @(posedge Clock or negedge RxReset)begin if (~RxReset) ClrRxRdy <= 0; else ClrRxRdy <= (ReadDRR | (ClrRxRdy & RxRdyReg));end//// generate RxRdy flag//always @(posedge NRxClock or negedge RxReset)begin if (~RxReset) RxRdyReg <= 0; else RxRdyReg <= (LoadDRR | (RxRdyReg & ~ClrRxRdy));endalways @(RxRdyReg or ClrRxRdy or ReadDRR)begin RxRdy = RxRdyReg & ~(ClrRxRdy | ReadDRR);end//// generate receive interrupt on load DRR//always @(posedge Clock)begin RINT <= LoadDRR;endendmodule⌨️ 快捷键说明
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