m3s054ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Wait-State Decoder
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.001

// m3s054ct
// M320C50 Decoder for number of wait-states in external access.
// This decode is put in a separate block to prevent the synthesiser
// from mixing in the Access control signals.

// PCount is the number of wait-states in a program memory access.
// DCount is the number of wait-states in a data memory access.
// ICount is the number of wait-states in an I/O access.


module m3s054ct (PDWSR, IOWSR, CWSR,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo, PAddr,
  PCount, DWCount, DRCount, IWCount, IRCount);

    input [15:0] PDWSR, IOWSR;
    input  [4:0] CWSR;
    input  [2:0] DWAddrHi, DWAddrLo, DRAddrHi, DRAddrLo;
    input  [1:0] PAddr;
    output [2:0] PCount, DWCount, DRCount, IWCount, IRCount;

    reg [2:0] PCount, DWCount, DRCount, IWCount, IRCount;
    reg [1:0] PBits, DWBits, DRBits, IWBits, IRBits;
    reg [2:0] IOWAddrSel, IORAddrSel;
    reg       IWBit, IRBit;


// Program space wait-states
always @(PAddr or PDWSR or CWSR)
begin
    case (PAddr)
        0: PBits = PDWSR[1:0];
        1: PBits = PDWSR[3:2];
        2: PBits = PDWSR[5:4];
        3: PBits = PDWSR[7:6];
    endcase
    if (CWSR[0] & PBits[1])
        PCount = {PBits[0],2'b11};
    else
        PCount = {1'b0,PBits};
end


// Data space wait-states
always @(DWAddrHi or PDWSR or CWSR)
begin
    case (DWAddrHi[2:1])
        0: DWBits = PDWSR[9:8];
        1: DWBits = PDWSR[11:10];
        2: DWBits = PDWSR[13:12];
        3: DWBits = PDWSR[15:14];
    endcase
    if (CWSR[1] & DWBits[1])
        DWCount = {DWBits[0],2'b11};
    else
        DWCount = {1'b0,DWBits};
end
always @(DRAddrHi or PDWSR or CWSR)
begin
    case (DRAddrHi[2:1])
        0: DRBits = PDWSR[9:8];
        1: DRBits = PDWSR[11:10];
        2: DRBits = PDWSR[13:12];
        3: DRBits = PDWSR[15:14];
    endcase
    if (CWSR[1] & DRBits[1])
        DRCount = {DRBits[0],2'b11};
    else
        DRCount = {1'b0,DRBits};
end


// IO space wait-states
always @(DWAddrHi or DWAddrLo or IOWSR or CWSR)
begin
    if (CWSR[4])
        IOWAddrSel = DWAddrHi;
    else
        IOWAddrSel = DWAddrLo;
    case (IOWAddrSel)
        0: IWBits = IOWSR[1:0];
        1: IWBits = IOWSR[3:2];
        2: IWBits = IOWSR[5:4];
        3: IWBits = IOWSR[7:6];
        4: IWBits = IOWSR[9:8];
        5: IWBits = IOWSR[11:10];
        6: IWBits = IOWSR[13:12];
        7: IWBits = IOWSR[15:14];
    endcase
    IWBit = (IOWAddrSel[2] & CWSR[3]) | (~IOWAddrSel[2] & CWSR[2]);
    if (IWBit & IWBits[1])
        IWCount = {IWBits[0],2'b11};
    else
        IWCount = {1'b0,IWBits};
end
always @(DRAddrHi or DRAddrLo or IOWSR or CWSR)
begin
    if (CWSR[4])
        IORAddrSel = DRAddrHi;
    else
        IORAddrSel = DRAddrLo;
    case (IORAddrSel)
        0: IRBits = IOWSR[1:0];
        1: IRBits = IOWSR[3:2];
        2: IRBits = IOWSR[5:4];
        3: IRBits = IOWSR[7:6];
        4: IRBits = IOWSR[9:8];
        5: IRBits = IOWSR[11:10];
        6: IRBits = IOWSR[13:12];
        7: IRBits = IOWSR[15:14];
    endcase
    IRBit = (IORAddrSel[2] & CWSR[3]) | (~IORAddrSel[2] & CWSR[2]);
    if (IRBit & IRBits[1])
        IRCount = {IRBits[0],2'b11};
    else
        IRCount = {1'b0,IRBits};
end


endmodule