m3s006ct.v

这是16位定点dsp源代码。已仿真和综合过了

        NextARPBPipe2 = ARPBPipe1;
    end
end
else
begin
    NextARPPipe1 = ARPPipe1;
    NextARPPipe2 = ARPPipe2;
    NextARPBPipe1 = ARPBPipe1;
    NextARPBPipe2 = ARPBPipe2;
end

// Registers
m3s052ct U2 (Clock, Reset, MemCycle, MemCycle1, NextARCR, NextIndex,
  NextARPPipe1, NextARPPipe2, NextARPBPipe1, NextARPBPipe2,
  NextSARPipe1, NextSARPipe2, NextARTC, NextARZ, NextSuppLdARP,
  NextARP, NextARPB, NextCBSR1, NextCBSR2, NextCBER1, NextCBER2, NextCBCR,
  NextReadAuxReg, NextWriteAuxReg,
  NextAuxRegister0, NextAuxRegister1, NextAuxRegister2, NextAuxRegister3,
  NextAuxRegister4, NextAuxRegister5, NextAuxRegister6, NextAuxRegister7,
  ARCR, Index, ARPPipe1, ARPPipe2, ARPBPipe1, ARPBPipe2,
  SARPipe1, SARPipe2, ARTC, ARZ, SuppLdARP, ARP, ARPB,
  CBSR1, CBSR2, CBER1, CBER2, CBCR, ReadAuxReg, WriteAuxReg,
  AuxRegister0, AuxRegister1, AuxRegister2, AuxRegister3,
  AuxRegister4, AuxRegister5, AuxRegister6, AuxRegister7);

// Auxillary register read pointer
always @(ARAUCntrl or SuppLdARP or ARP or IpBus)
    if ((ARAUCntrl[0] | ARAUCntrl[1]) & ~SuppLdARP) ARPointer = IpBus[15:13];
    else ARPointer = ARP;

// Auxillary register bank reads
always @(ARWriteAddr or MMRegCntrl or ARWriteData
  or AuxRegister0 or AuxRegister1 or AuxRegister2 or AuxRegister3
  or AuxRegister4 or AuxRegister5 or AuxRegister6 or AuxRegister7)
begin
    if ((ARWriteAddr == 0) & MMRegCntrl[0])
        OpPortB0 = ARWriteData;
    else
        OpPortB0 = AuxRegister0;
    if ((ARWriteAddr == 1) & MMRegCntrl[0])
        OpPortB1 = ARWriteData;
    else
        OpPortB1 = AuxRegister1;
    if ((ARWriteAddr == 2) & MMRegCntrl[0])
        OpPortB2 = ARWriteData;
    else
        OpPortB2 = AuxRegister2;
    if ((ARWriteAddr == 3) & MMRegCntrl[0])
        OpPortB3 = ARWriteData;
    else
        OpPortB3 = AuxRegister3;
    if ((ARWriteAddr == 4) & MMRegCntrl[0])
        OpPortB4 = ARWriteData;
    else
        OpPortB4 = AuxRegister4;
    if ((ARWriteAddr == 5) & MMRegCntrl[0])
        OpPortB5 = ARWriteData;
    else
        OpPortB5 = AuxRegister5;
    if ((ARWriteAddr == 6) & MMRegCntrl[0])
        OpPortB6 = ARWriteData;
    else
        OpPortB6 = AuxRegister6;
    if ((ARWriteAddr == 7) & MMRegCntrl[0])
        OpPortB7 = ARWriteData;
    else
        OpPortB7 = AuxRegister7;
end

// AuxRegFile multiplexer
always @(ARPointer or
    AuxRegister0 or AuxRegister1 or AuxRegister2 or AuxRegister3 or 
    AuxRegister4 or AuxRegister5 or AuxRegister6 or AuxRegister7)
    case (ARPointer)
        0: AuxRegFile = AuxRegister0;
        1: AuxRegFile = AuxRegister1;
        2: AuxRegFile = AuxRegister2;
        3: AuxRegFile = AuxRegister3;
        4: AuxRegFile = AuxRegister4;
        5: AuxRegFile = AuxRegister5;
        6: AuxRegFile = AuxRegister6;
        7: AuxRegFile = AuxRegister7;
    endcase

// Suppress LST load of ARP if previous cycle modified the ARP
always @(ARAUCntrl or SuppLdARP or AdvCycle)
if (AdvCycle) NextSuppLdARP = ARAUCntrl[7];
else NextSuppLdARP = SuppLdARP;

// Pointer register writes
always @(ARAUCntrl or SuppLdARP or ContextRestore or IpBus or ARP_C or ARP
  or ARPB_C or ARPB)
begin
    if (ARAUCntrl[7] & ~ARAUCntrl[21]) NextARP = ARAUCntrl[17:15];
    else if ((ARAUCntrl[0] | ARAUCntrl[1]) & ~SuppLdARP) NextARP = IpBus[15:13];
    else if (ContextRestore) NextARP = ARP_C;
    else NextARP = ARP;
    if (ARAUCntrl[7] & ~ARAUCntrl[21]) NextARPB = ARP;
    else if (ARAUCntrl[1] & ~SuppLdARP) NextARPB = IpBus[15:13];
    else if (ContextRestore) NextARPB = ARPB_C;
    else NextARPB = ARPB;
end

// Other register writes
always @(ARAUCntrl or NDX or ARWriteAddr) // Index/ARCR load from LAR
    LdWithLAR = (ARAUCntrl[4] | ARAUCntrl[5]) & (ARWriteAddr==0) & ~NDX;
always @(ARAUCntrl or NDX or ARP) // Index/ARCR load from LAR
    LdWithMAR = ARAUCntrl[6] & (ARP==0) & ~NDX;
always @(MMRegCntrl or iMMR or ContextRestore or LdWithLAR or LdWithMAR
      or IpBus or DataWrite or ARCR or Index or ARCR_C or Index_C or ARAU)
begin
    if (LdWithMAR) NextARCR = ARAU;
    else if ((MMRegCntrl[2] & iMMR) | LdWithLAR)
        NextARCR = IpBus;
    else if (MMRegCntrl[2] & ~iMMR) NextARCR = DataWrite;
    else if (ContextRestore) NextARCR = ARCR_C;
    else NextARCR = ARCR;

    if (LdWithMAR) NextIndex = ARAU;
    else if ((MMRegCntrl[1] & iMMR) | LdWithLAR)
        NextIndex = IpBus;
    else if (MMRegCntrl[1] & ~iMMR) NextIndex = DataWrite;
    else if (ContextRestore) NextIndex = Index_C;
    else NextIndex = Index;
end

always @(posedge Clock)
if (ContextSave)
begin
    ARP_C <= ARP;
    ARPB_C <= ARPB;
    ARCR_C <= ARCR;
    Index_C <= Index;
end

// Circular buffer registers
always @(Reset or MMRegCntrl or iMMR or DataWrite or IpBus
       or CBSR1 or CBSR2 or CBER1 or CBER2 or CBCR)
begin
    if (MMRegCntrl[3] & iMMR) NextCBSR1 = IpBus;
    else if (MMRegCntrl[3] & ~iMMR) NextCBSR1 = DataWrite;
    else NextCBSR1 = CBSR1;
    if (MMRegCntrl[4] & iMMR) NextCBER1 = IpBus;
    else if (MMRegCntrl[4] & ~iMMR) NextCBER1 = DataWrite;
    else NextCBER1 = CBER1;
    if (MMRegCntrl[5] & iMMR) NextCBSR2 = IpBus;
    else if (MMRegCntrl[5] & ~iMMR) NextCBSR2 = DataWrite;
    else NextCBSR2 = CBSR2;
    if (MMRegCntrl[6] & iMMR) NextCBER2 = IpBus;
    else if (MMRegCntrl[6] & ~iMMR) NextCBER2 = DataWrite;
    else NextCBER2 = CBER2;
    if (Reset) NextCBCR = 8'h77;
    else if (MMRegCntrl[7] & iMMR) NextCBCR = IpBus[7:0];
    else if (MMRegCntrl[7] & ~iMMR) NextCBCR = DataWrite[7:0];
    else NextCBCR = CBCR;
end

// Circular buffer end comparison
always @(CBCR or CBER1 or CBER2 or AuxReg or ARP)
begin
    if ((CBCR[2:0] == ARP) & CBCR[3]) CmprBuff1 = 1;
    else CmprBuff1 = 0;
    if ((CBCR[6:4] == ARP) & CBCR[7]) CmprBuff2 = 1;
    else CmprBuff2 = 0;

    if (CmprBuff2) CBR = CBER2;
    else CBR = CBER1;

    if (AuxReg == CBR) EndofBuff = 1;
    else EndofBuff = 0;

    LdCB1 = CmprBuff1 & EndofBuff;
    LdCB2 = CmprBuff2 & EndofBuff;
end

// Index and ARCR multiplexers for the multiplier
always @(MMRegCntrl or iMMR or LdWithLAR or ContextRestore
        or IpBus or DataWrite or Index or ARCR or Index_C or ARCR_C)
begin
    case ({LdWithLAR,MMRegCntrl[2],iMMR,ContextRestore})
        0: SourceARCR = ARCR;
        1: SourceARCR = ARCR_C;
        2: SourceARCR = ARCR;
        3: SourceARCR = ARCR_C;
        4: SourceARCR = DataWrite;
        5: SourceARCR = DataWrite;
        default: SourceARCR = IpBus;
    endcase
    case ({LdWithLAR,MMRegCntrl[1],iMMR,ContextRestore})
        0: SourceIndex = Index;
        1: SourceIndex = Index_C;
        2: SourceIndex = Index;
        3: SourceIndex = Index_C;
        4: SourceIndex = DataWrite;
        5: SourceIndex = DataWrite;
        default: SourceIndex = IpBus;
    endcase
end

// ARAU
m3s016ct U1 (AuxReg, SourceIndex, SourceARCR, ShortImm, CBSR1, CBSR2,
     ARAUCntrl[13:8], LdCB1, LdCB2, ARAU, C, Z);

// Generate ReadAuxReg output
always @(AdvCycle or ARAUCntrl or AuxReg or ReadAuxReg or DFCAuxStall)
    if ((AdvCycle | DFCAuxStall) & ~ARAUCntrl[21])
        NextReadAuxReg = AuxReg;
    else
        NextReadAuxReg = ReadAuxReg;

// Generate WriteAuxReg output
always @(AdvCycle or ARAUCntrl or ReadAuxReg or WriteAuxReg)
    if (AdvCycle & ~ARAUCntrl[21])
        NextWriteAuxReg = ReadAuxReg;
    else
        NextWriteAuxReg = WriteAuxReg;

// Set ARTC according to ARAU output flags and CM control bits
// ARTC pipelined before being loaded into TC
always @(C or Z or ARAUCntrl)
    case (ARAUCntrl[16:15])
    2'b00: NextARTC = Z;      // AR(ARP) = ARCR
    2'b01: NextARTC = ~C;     // AR(ARP) < ARCR
    2'b10: NextARTC = C & ~Z; // AR(ARP) > ARCR
    2'b11: NextARTC = ~Z;     // AR(ARP) != ARCR
    endcase

// Zero detect for AR(ARP)
always @(AdvCycle or AuxReg or ARZ)
if (AdvCycle) NextARZ = !AuxReg;
else NextARZ = ARZ;

// DataWrite ARP output mux
always @(ARAUCntrl or ARPPipe2 or ARPBPipe2)
if (ARAUCntrl[3]) ARPOp = ARPBPipe2;
else ARPOp = ARPPipe2;

// Register reads
assign DataWrite[15:13] = ((ARAUCntrl[3] | ARAUCntrl[2]) & ~DMAMode)
    ? ARPOp : 3'bZ;
assign DataWrite = (SARPipe2[16] & ~DMAMode) ? SARPipe2[15:0] : 16'bZ;

// DataRead mux
always @(ARReadAddr or OpPortB0 or OpPortB1 or OpPortB2 or OpPortB3 or
    OpPortB4 or OpPortB5 or OpPortB6 or OpPortB7)
    case (ARReadAddr)
        0: PortB = OpPortB0;
        1: PortB = OpPortB1;
        2: PortB = OpPortB2;
        3: PortB = OpPortB3;
        4: PortB = OpPortB4;
        5: PortB = OpPortB5;
        6: PortB = OpPortB6;
        7: PortB = OpPortB7;
    endcase
always @(MMRegCntrl or PortB or SourceIndex or SourceARCR or
    NextCBSR1 or NextCBER1 or NextCBSR2 or NextCBER2 or NextCBCR)
    DataReadMux = ({16{MMRegCntrl[8]}} & PortB) |
                  ({16{MMRegCntrl[9]}} & SourceIndex) |
                  ({16{MMRegCntrl[10]}} & SourceARCR) |
                  ({16{MMRegCntrl[11]}} & NextCBSR1) |
                  ({16{MMRegCntrl[12]}} & NextCBER1) |
                  ({16{MMRegCntrl[13]}} & NextCBSR2) |
                  ({16{MMRegCntrl[14]}} & NextCBER2) |
                  ({16{MMRegCntrl[15]}} & {8'hFF,NextCBCR});

assign DataRead = (MMRegCntrl[15:8] != 0) ?
    DataReadMux : 16'bZ;
endmodule