m3s006ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Auxillary Registers
// Copyright Mentor Graphics Corporation and Licensors 1998
// V1.109

// Revision history
// V1.109 - 2 December 1996
//          LastSupp replaced by DFCAuxStall.
// V1.108 - 20 November 1996
//          Number of tri-state drivers reduced.
// V1.107 - NextReadAuxReg update modified to fix BLDD bug

// m3s006ct
// M320C50 Auxillary registers, pointer and arithmetic unit.
// Provides:
//     eight 16-bit auxillary registers
//     an auxillary register pointer and pointer buffer
//     an auxillary register compare register
//     an index register
//     a 16-bit arithmetic unit
//
// MMRegCntrl usage:
//    0 : Write AR
//    1 : Write Index reg
//    2 : Write ARCR
//    3 : Write CBSR1
//    4 : Write CBER1
//    5 : Write CBSR2
//    6 : Write CBER2
//    7 : Write CBCR
//    8 : Read AR
//    9 : Read Index reg
//   10 : Read ARCR
//   11 : Read CBSR1
//   12 : Read CBER1
//   13 : Read CBSR2
//   14 : Read CBER2
//   15 : Read CBCR
//
// ARAUCntrl usage:
//    0 : Write ST0
//    1 : Write ST1
//    2 : Read ARP
//    3 : Read ARPB
//    4 : LAR from data bus
//    5 : LAR from prog bus
//    6 : Modify AR
//    7 : Load ARP
//    8 : Aux reg compare with ARCR
//    9 : Short Immediate operand
// 13:10 : ARAU control
//   14 : Store Aux reg
// 17:15 : Next ARP / CM (used by CMPR instruction)
// 20:18 : Aux reg store address
//    21 : Stall Aux register updates
//
// ReadAuxReg and WriteAuxReg are the current read and write Auxillary Registers (AR(ARP)).
// WriteAuxReg is delayed by one cycle.
// ARZ is 1 if AR(ARP) = 0
// ARTC is the value to load into the TC flag when comparing AR(ARP) with ARCR

`define C_NUMAUXREGS 8


module m3s006ct (IpBus, WriteAddr, ReadAddr, ShortImm, ARAddr,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    Clock, Reset, AdvCycle, MemCycle, MemCycle1, ContextSave, ContextRestore,
    MMRegCntrl, ARAUCntrl, iMMR, NDX, DMAMode, DFCAuxStall,
    NextReadAuxReg, NextWriteAuxReg,
    DataWrite, DataRead, ARZ, ARTC);

    input  [15:0] IpBus;
    input   [2:0] WriteAddr, ReadAddr;
    input   [7:0] ShortImm;
    input   [2:0] ARAddr;
    input         Clock, Reset, AdvCycle, MemCycle, MemCycle1;
    input         iMMR, NDX, DMAMode, DFCAuxStall, ContextSave, ContextRestore;
    input  [15:0] MMRegCntrl;
    input  [21:0] ARAUCntrl;
    inout  [15:0] DataWrite;
    output [15:0] NextReadAuxReg, NextWriteAuxReg, DataRead;
    output        ARZ, ARTC;

    reg [15:0] AuxRegFile, PortB;
    tri [15:0] DataWrite;
    reg  [2:0] NextARP, NextARPB, ARP_C, ARPB_C, ARPointer, ARPOp;
    wire [2:0] ARP, ARPB, ARPPipe1, ARPBPipe1, ARPPipe2, ARPBPipe2;
    reg  [2:0] NextARPPipe1, NextARPBPipe1, NextARPPipe2, NextARPBPipe2;
    wire [15:0] AuxRegister0, AuxRegister1, AuxRegister2, AuxRegister3;
    wire [15:0] AuxRegister4, AuxRegister5, AuxRegister6, AuxRegister7;
    reg [15:0] NextAuxRegister0, NextAuxRegister1, NextAuxRegister2, NextAuxRegister3;
    reg [15:0] NextAuxRegister4, NextAuxRegister5, NextAuxRegister6, NextAuxRegister7;
    reg [15:0] OpPortB0, OpPortB1, OpPortB2, OpPortB3;
    reg [15:0] OpPortB4, OpPortB5, OpPortB6, OpPortB7;
    wire [15:0] ReadAuxReg, WriteAuxReg;
    reg [15:0] AuxReg, NextReadAuxReg, NextWriteAuxReg;
    wire [15:0] ARCR, Index;
    reg [15:0] ARCR_C, Index_C, NextARCR, NextIndex;
    reg [15:0] SourceIndex, SourceARCR;
    reg [15:0] NextCBSR1, NextCBSR2, NextCBER1, NextCBER2;
    reg  [7:0] NextCBCR;
    reg        NextARZ, NextARTC;
    reg  [2:0] ARReadAddr, ARWriteAddr;
    reg        ARWriteEnable, LdWithLAR, LdWithMAR;
    reg [15:0] ARWriteData, CBR, DataReadMux;
    wire [16:0] SARPipe1, SARPipe2;
    reg [16:0] NextSARPipe1, NextSARPipe2;
    reg        CmprBuff1, CmprBuff2, EndofBuff, LdCB1, LdCB2;
    reg        NextSuppLdARP;
    wire [15:0] ARAU, CBSR1, CBSR2, CBER1, CBER2;
    wire  [7:0] CBCR;
    wire       C, Z, ARTC, ARZ, SuppLdARP;

    integer n;

// Write port multiplexers
always @(WriteAddr or ARAddr or ARP or MMRegCntrl or ARAUCntrl or IpBus
    or iMMR or DataWrite or ARAU or AuxRegFile)
begin
    if (MMRegCntrl[0]) ARWriteAddr = WriteAddr;
    else ARWriteAddr = ARAddr;
    if (MMRegCntrl[0] & ~iMMR) ARWriteData = DataWrite;
    else ARWriteData = IpBus;
    ARWriteEnable = MMRegCntrl[0] | ARAUCntrl[4] | ARAUCntrl[5];
    if ((ARWriteAddr == ARP) & ARWriteEnable)
        AuxReg = IpBus;
    else AuxReg = AuxRegFile;
end


// Auxillary register bank writes
always @(ARAUCntrl or ARP or ARWriteEnable or ARWriteAddr or ARAU or ARWriteData
  or AuxRegister0 or AuxRegister1 or AuxRegister2 or AuxRegister3
  or AuxRegister4 or AuxRegister5 or AuxRegister6 or AuxRegister7)
    if (~ARAUCntrl[21])
    begin
        if (ARAUCntrl[6] && (ARP == 0)) NextAuxRegister0 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 0)) NextAuxRegister0 = ARWriteData;
        else NextAuxRegister0 = AuxRegister0;
        if (ARAUCntrl[6] && (ARP == 1)) NextAuxRegister1 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 1)) NextAuxRegister1 = ARWriteData;
        else NextAuxRegister1 = AuxRegister1;
        if (ARAUCntrl[6] && (ARP == 2)) NextAuxRegister2 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 2)) NextAuxRegister2 = ARWriteData;
        else NextAuxRegister2 = AuxRegister2;
        if (ARAUCntrl[6] && (ARP == 3)) NextAuxRegister3 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 3)) NextAuxRegister3 = ARWriteData;
        else NextAuxRegister3 = AuxRegister3;
        if (ARAUCntrl[6] && (ARP == 4)) NextAuxRegister4 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 4)) NextAuxRegister4 = ARWriteData;
        else NextAuxRegister4 = AuxRegister4;
        if (ARAUCntrl[6] && (ARP == 5)) NextAuxRegister5 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 5)) NextAuxRegister5 = ARWriteData;
        else NextAuxRegister5 = AuxRegister5;
        if (ARAUCntrl[6] && (ARP == 6)) NextAuxRegister6 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 6)) NextAuxRegister6 = ARWriteData;
        else NextAuxRegister6 = AuxRegister6;
        if (ARAUCntrl[6] && (ARP == 7)) NextAuxRegister7 = ARAU;
        else if (ARWriteEnable && (ARWriteAddr == 7)) NextAuxRegister7 = ARWriteData;
        else NextAuxRegister7 = AuxRegister7;
    end
    else
    begin
        NextAuxRegister0 = AuxRegister0;
        NextAuxRegister1 = AuxRegister1;
        NextAuxRegister2 = AuxRegister2;
        NextAuxRegister3 = AuxRegister3;
        NextAuxRegister4 = AuxRegister4;
        NextAuxRegister5 = AuxRegister5;
        NextAuxRegister6 = AuxRegister6;
        NextAuxRegister7 = AuxRegister7;
    end

// Read port multiplexer
always @(ReadAddr or ARAddr or MMRegCntrl)
begin
    if (MMRegCntrl[8]) ARReadAddr = ReadAddr;
    else ARReadAddr = ARAddr;
end

// SAR output pipeline
always @(AdvCycle or Reset or ARAUCntrl or ARWriteAddr or ARWriteEnable
  or SARPipe1 or SARPipe2 or IpBus
  or AuxRegister0 or AuxRegister1 or AuxRegister2 or AuxRegister3
  or AuxRegister4 or AuxRegister5 or AuxRegister6 or AuxRegister7)
begin
    if (AdvCycle & ARAUCntrl[14])
    begin
        if ((ARAUCntrl[20:18] == ARWriteAddr) & ARWriteEnable)
            NextSARPipe1[15:0] = IpBus;
        else
        case (ARAUCntrl[20:18])
            0: NextSARPipe1[15:0] = AuxRegister0;
            1: NextSARPipe1[15:0] = AuxRegister1;
            2: NextSARPipe1[15:0] = AuxRegister2;
            3: NextSARPipe1[15:0] = AuxRegister3;
            4: NextSARPipe1[15:0] = AuxRegister4;
            5: NextSARPipe1[15:0] = AuxRegister5;
            6: NextSARPipe1[15:0] = AuxRegister6;
            7: NextSARPipe1[15:0] = AuxRegister7;
        endcase
        NextSARPipe1[16] = 1;
    end
    else
    begin
        NextSARPipe1[15:0] = SARPipe1[15:0];
        NextSARPipe1[16] = SARPipe1[16] & ~(AdvCycle | Reset);
    end
    if (AdvCycle)
        NextSARPipe2 = SARPipe1;
    else
        NextSARPipe2 = SARPipe2;
end

// ARP, ARPB output pipeline
always @(AdvCycle or ARAUCntrl or SuppLdARP or IpBus or ARP or ARPB
  or ARPPipe1 or ARPPipe2 or ARPBPipe1 or ARPBPipe2)
if (AdvCycle)
begin
    if ((ARAUCntrl[0] | ARAUCntrl[1]) & ~SuppLdARP)
    begin
        NextARPPipe1 = IpBus[15:13];
        NextARPPipe2 = IpBus[15:13];
    end
    else
    begin
        NextARPPipe1 = ARP;
        NextARPPipe2 = ARPPipe1;
    end
    if (ARAUCntrl[1] & ~SuppLdARP)
    begin
        NextARPBPipe1 = IpBus[15:13];
        NextARPBPipe2 = IpBus[15:13];
    end
    else
    begin
        NextARPBPipe1 = ARPB;