m3s052ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Indirect Addressing Control Latches
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.003

// Revision history
// V1.003 - 2 December 1996
//        - LastSupp removed.
// V1.002 - LastSupp latch added to fix bug with BLDD instructions

// m3s052ct
// M320C50 Latches for use with indirect addressing.
// These latches, together with the MemCycle control line are in a
// separate block to prevent the synthesiser from mixing MemCycle with
// the decoding logic.

module m3s052ct (Clock, Reset, MemCycle, MemCycle1, NextARCR, NextIndex,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  NextARPPipe1, NextARPPipe2, NextARPBPipe1, NextARPBPipe2,
  NextSARPipe1, NextSARPipe2, NextARTC, NextARZ, NextSuppLdARP,
  NextARP, NextARPB, NextCBSR1, NextCBSR2, NextCBER1, NextCBER2, NextCBCR,
  NextReadAuxReg, NextWriteAuxReg,
  NextAuxRegister0, NextAuxRegister1, NextAuxRegister2, NextAuxRegister3,
  NextAuxRegister4, NextAuxRegister5, NextAuxRegister6, NextAuxRegister7,
  ARCR, Index, ARPPipe1, ARPPipe2, ARPBPipe1, ARPBPipe2,
  SARPipe1, SARPipe2, ARTC, ARZ, SuppLdARP, ARP, ARPB,
  CBSR1, CBSR2, CBER1, CBER2, CBCR, ReadAuxReg, WriteAuxReg,
  AuxRegister0, AuxRegister1, AuxRegister2, AuxRegister3,
  AuxRegister4, AuxRegister5, AuxRegister6, AuxRegister7);

    input         Clock, Reset, MemCycle, MemCycle1;
    input         NextARTC, NextARZ, NextSuppLdARP;
    input  [15:0] NextARCR, NextIndex, NextCBSR1, NextCBSR2, NextCBER1, NextCBER2;
    input   [7:0] NextCBCR;
    input   [2:0] NextARP, NextARPB;
    input   [2:0] NextARPPipe1, NextARPPipe2, NextARPBPipe1, NextARPBPipe2;
    input  [16:0] NextSARPipe1, NextSARPipe2;
    input  [15:0] NextAuxRegister0, NextAuxRegister1, NextAuxRegister2, NextAuxRegister3;
    input  [15:0] NextAuxRegister4, NextAuxRegister5, NextAuxRegister6, NextAuxRegister7;
    input  [15:0] NextReadAuxReg, NextWriteAuxReg;
    output [15:0] ARCR, Index, CBSR1, CBSR2, CBER1, CBER2;
    output  [2:0] ARP, ARPB, ARPPipe1, ARPPipe2, ARPBPipe1, ARPBPipe2;
    output [16:0] SARPipe1, SARPipe2;
    output [15:0] AuxRegister0, AuxRegister1, AuxRegister2, AuxRegister3;
    output [15:0] AuxRegister4, AuxRegister5, AuxRegister6, AuxRegister7;
    output [15:0] ReadAuxReg, WriteAuxReg;
    output  [7:0] CBCR;
    output        ARTC, ARZ, SuppLdARP;

    reg [15:0] ARCR, Index, CBSR1, CBSR2, CBER1, CBER2;
    reg  [2:0] ARP, ARPB, ARPPipe1, ARPPipe2, ARPBPipe1, ARPBPipe2;
    reg [16:0] SARPipe1, SARPipe2;
    reg [15:0] AuxRegister0, AuxRegister1, AuxRegister2, AuxRegister3;
    reg [15:0] AuxRegister4, AuxRegister5, AuxRegister6, AuxRegister7;
    reg [15:0] ReadAuxReg, WriteAuxReg;
    reg  [7:0] CBCR;
    reg        ARTC, ARTC1, ARZ, SuppLdARP;


always @(posedge Clock or posedge Reset)
if (Reset)
begin
    SuppLdARP <= 0;
    ARP <= 0;
    ARPB <= 0;
end
else if (MemCycle)
begin
    SuppLdARP <= NextSuppLdARP;
    ARP <= NextARP;
    ARPB <= NextARPB;
end

always @(posedge Clock)
if (MemCycle)
begin
    ARCR <= NextARCR;
    Index <= NextIndex;
    ARPPipe1 <= NextARPPipe1;
    ARPPipe2 <= NextARPPipe2;
    ARPBPipe1 <= NextARPBPipe1;
    ARPBPipe2 <= NextARPBPipe2;
    SARPipe1 <= NextSARPipe1;
    SARPipe2 <= NextSARPipe2;
    ARTC1 <= NextARTC;
    ARTC <= ARTC1;
    ARZ <= NextARZ;
    CBSR1 <= NextCBSR1;
    CBER1 <= NextCBER1;
    CBSR2 <= NextCBSR2;
    CBER2 <= NextCBER2;
    CBCR <= NextCBCR;
    ReadAuxReg <= NextReadAuxReg;
    WriteAuxReg <= NextWriteAuxReg;
end

always @(posedge Clock)
if (MemCycle1)
begin
    AuxRegister0 <= NextAuxRegister0;
    AuxRegister1 <= NextAuxRegister1;
    AuxRegister2 <= NextAuxRegister2;
    AuxRegister3 <= NextAuxRegister3;
    AuxRegister4 <= NextAuxRegister4;
    AuxRegister5 <= NextAuxRegister5;
    AuxRegister6 <= NextAuxRegister6;
    AuxRegister7 <= NextAuxRegister7;
end

endmodule