mc50_control.v

这是16位定点dsp源代码。已仿真和综合过了

module mc50_control(NRD, NWR, NDS, NPS, NIS,
CLKIN1,NCLKI,NHOE,NRD_O,NWR_O,NDS_O,NPS_O,NIS_O,
OA,A,AI,NDEN,OD,RNW,RNWO,RNWI,NSTB,NBR_O,NBR,NBRI,
NCLKXE,CLKX,CLKXO,CLKXI,NTCLKXE, TCLKXO, TCLKX,TCLKXI,NDXE,DX,DX_O,
NTDXE, TDX,TDX_O,NTADDE, TADD, TFSR,NFSXE, FSXO, FSX,FSXI,
NTFSXE, TFSXO, TFSX,TFSXI,X1,DI,D,NSTRBO,NNMI,NMI,CLKO,CLKOUT1,
TDO,SRdy,PRdy);

input NRD, NWR, NDS, NPS, NIS;
input CLKIN1,NHOE,NDEN,RNWO;
input [15:0] OA,OD;
input NBR,NCLKXE,CLKXO,NTCLKXE,TCLKXO;
input NDXE,DX,NTDXE,TDX;
input NTADDE,TADD,NFSXE,FSXO,NTFSXE,TFSXO,NSTRBO;
input NMI,CLKO;

output NCLKI,NRD_O,NWR_O,NDS_O,NPS_O,NIS_O;
output [14:0] AI;
output [15:0] DI;
output RNWI,NBRI,CLKXI,TCLKXI;
output DX_O,TDX_O;
output FSXI,TFSXI,X1;
output NNMI,CLKOUT1,TDO,SRdy,PRdy;

inout [15:0] A,D;
inout RNW,NSTB,NBR_O,CLKX,TCLKX;
inout TFSR,FSX,TFSX;

wire CLKIN1,NHOE,NDEN,RNWO;
wire [15:0] OA,OD;
wire NBR,NCLKXE,CLKXO,NTCLKXE,TCLKXO;
wire NDXE,DX,NTDXE,TDX;
wire NTADDE,TADD,NFSXE,FSXO,NTFSXE,TFSXO,NSTRBO;
wire NMI,CLKO;


wire NCLKI,NRD_O,NWR_O,NDS_O,NPS_O,NIS_O;
wire [15:0] A,D,DI;
wire [14:0] AI;
wire RNW,RNWI,NSTB,NBR_O,NBRI;
wire CLKX,CLKXI,TCLKX,TCLKXI;
wire DX_O,TDX_O;
wire TFSR,TFSRI,FSX,FSXI,TFSX,TFSXI,X1;
wire NNMI,CLKOUT1;
wire TDO,SRdy,PRdy;

assign CLKOUT1 = CLKO;

assign A[15:0] = (NHOE ? 16'bZ : OA[15:0]);
assign AI = A[14:0];

assign D[15:0] = (NDEN ? 16'bZ : OD[15:0]);
//assign D[15:0] = OD[15:0];
assign DI[15:0] = D[15:0];

assign RNW = (NHOE ? 1'bZ : RNWO);
assign RNWI = RNW;

assign NSTB = (NHOE ? 1'bZ : NSTRBO);
assign NSTRBI = NSTB;

assign NBR_O = (NHOE ? 1'bZ : NBR);
assign NBRI = NBR_O;

assign CLKX = (NCLKXE ? 1'bZ : CLKXO);
assign CLKXI = CLKX;

assign TCLKX = (NTCLKXE ? 1'bZ : TCLKXO);
assign TCLKXI = TCLKX;

assign DX_O = (NDXE ? 1'bZ : DX);
assign TDX_O = (NTDXE ? 1'bZ : TDX);

assign TFSR = (NTADDE ? 1'bZ : TADD);
assign TFSRI = TFSR;

assign FSX = (NFSXE ? 1'bZ : FSXO);
assign FSXI = FSX; 

assign TFSX = (NTFSXE ? 1'bZ : TFSXO);
assign TFSXI = TFSX; 

assign X1 = (CLKIN1 ? 1'b0 : 1'bZ);

assign NNMI = NMI;
//
// Buffers input
//
assign NCLKI = !CLKIN1;

//
// Buffers output
//
assign NRD_O = (NHOE ? 1'bZ : NRD);
assign NWR_O = (NHOE ? 1'bZ : NWR);
assign NDS_O = (NHOE ? 1'bZ : NDS);
assign NPS_O = (NHOE ? 1'bZ : NPS);
assign NIS_O = (NHOE ? 1'bZ : NIS);
//
// Non driven signals
// default setting
//
//initial
//begin
//    TDO = 1'bZ;    // JTAG scan test output
//    SRdy = 1'b1;   // Internal ready control
//    PRdy = 1'b1;   // 
//end
assign TDO = 1'bZ;
assign SRdy = 1'b1;
assign PRdy = 1'b1;


endmodule