m3s010ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Parallel Logic Unit
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.101

// Revision history
// V1.101 - 27 June 1997
//          Number of tri-state drivers reduced.

// m3s010ct
// M320C50 Parallel Logic Unit
// Performs logical operations (AND, OR, XOR) on two 16-bit input vectors.
// Outputs to the data bus and a control line indicating whether the result
// is equal to zero.
// The DBMR memory mapped register is included.
//
// One input to the LU is "DataBus" the other input is selcted from
// "ProgBus" or the DBMR register.
//
// As well as the 3 logical operations the output can also be taken directly
// from the "ProgBus" input, by-passing the LU.
//
// The "Zero" output is '1' when the LU output is zero.
//
// The logical operation is controlled by "Cntrl1", "Cntrl0" as follows:
//     Cntrl
//      1 0   Operation
//     ----------------
//      0 0   XOR
//      0 1   OR
//      1 0   AND
//      1 1   XOR
//
// "Cntrl2" selects "ProgBus" when 1, and DBMR when 0.
//
// Cntrl[3:5] select the output onto the data bus as follows
//     Cntrl[3] : LU
//     Cntrl[4] : ProgBus
//     Cntrl[5] : DBMR
//
// "Cntrl[6]" Loads the DBMR register from the Data bus.


module m3s010ct (ProgBus, DataBus, Cntrl, Clock, Reset, iMMR, DMAMode,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
     DataWrite, DataRead, Zero);
    input  [15:0] ProgBus, DataBus;
    input  [6:0]  Cntrl;
    input         Clock, Reset, iMMR, DMAMode;
    inout  [15:0] DataWrite;
    output [15:0] DataRead;
    output        Zero;

    reg [15:0] LU_Ip, LU_Op, DBMR, NextDBMR, DataWriteOp;
    reg Zero;

// DBMR register
always @(DBMR or Cntrl or Reset or iMMR or DataBus or DataWrite)
    if (Reset) NextDBMR = 16'b0;
    else if (Cntrl[6] & iMMR) NextDBMR = DataBus;
    else if (Cntrl[6] & ~iMMR) NextDBMR = DataWrite;
    else NextDBMR = DBMR;
always @(posedge Clock)
    DBMR <= NextDBMR;

// LU input select mux
always @(ProgBus or DBMR or Cntrl)
    if (Cntrl[2]) LU_Ip = ProgBus;
    else LU_Ip = DBMR;

// LU
always @(DataBus or LU_Ip or Cntrl)
begin
    case (Cntrl[1:0])
    2'b00: LU_Op = LU_Ip ^ DataBus;
    2'b01: LU_Op = LU_Ip | DataBus;
    2'b10: LU_Op = LU_Ip & DataBus;
    2'b11: LU_Op = LU_Ip ^ DataBus;
    endcase
    if (!LU_Op) Zero = 1;
    else Zero = 0;
end

// DataWrite output mux
always @(Cntrl or LU_Op or ProgBus)
    if (Cntrl[3]) DataWriteOp = LU_Op;
    else DataWriteOp = ProgBus;

// Output drivers
assign DataWrite = ((Cntrl[3] | Cntrl[4]) & ~DMAMode) ? DataWriteOp : 16'bZ;
assign DataRead = (Cntrl[5]) ? NextDBMR : 16'bZ;

endmodule