m3s003ct.v

来自「这是16位定点dsp源代码。已仿真和综合过了」· Verilog 代码 · 共 103 行

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Program Address Generator
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.202

// Revision history
// V1.202 - 16 December 1996
//          IFnEx input from Pipeline controller.
// V1.201 - 20 November 1996
//          Inputs for putting write data on ProgReadBus.
// V1.2   - 3 June 1996
//          New top level for program address generator to avoid
//          possible synthesis problems.
//          SetBRAF signal added, from m3s071ct.
// V1.105 - 10 May 1996

// m3s003ct
// M320C50 Program Address Generator

module m3s003ct (ProgBus, DataBus, IntPtr, IntNum, B0D, PD, DI,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    Clock, MemCycle, InsCycle, Reset, PACntrl, BMARRegCntrl, BrptRegCntrl, iMMR,
    MPNMC, CNF, RAM, BRAF, IFnEx, SetBRAF, ClrBRAF, iTBLW, DMAMode,
    PrProgValid, DpProgValid, SpProgValid, ExProgValid,
    SpRdWrDet,
    ProgAddr, DataWrite, PrDpReq, PrSpReq, PrPrReq, PrExReq,
    PwDpReq, PwSpReq, PwPrReq, PwExReq, ProgValid,
    DataRead, InsFetch, ProgRead);

    inout  [15:0] ProgBus, DataBus, DataWrite;
    input  [15:0] B0D, PD, DI;
    input   [4:0] IntPtr, IntNum;
    input         Clock, MemCycle, InsCycle, Reset;
    input  [18:0] PACntrl;
    input   [1:0] BMARRegCntrl;
    input   [5:0] BrptRegCntrl;
    input         MPNMC, CNF, RAM, BRAF, iTBLW, iMMR, DMAMode;
    input         PrProgValid, DpProgValid, SpProgValid, ExProgValid;
    input         SpRdWrDet, IFnEx;
    output [15:0] ProgAddr, DataRead, ProgRead;
    output        SetBRAF, ClrBRAF, ProgValid, InsFetch;
    output        PrDpReq, PrSpReq, PrPrReq, PrExReq;
    output        PwDpReq, PwSpReq, PwPrReq, PwExReq;

    wire [15:0] DFC, BMAR, NextBMAR, StackOut;
    wire        DFCProgEnab, StackDataEnab, StackWriteEnab;
    wire        BMARReadEnab, BMARProgEnab;
    tri  [15:0] DataRead;


// Program address generator
m3s071ct U1 (ProgBus, DataBus, IntPtr, IntNum, B0D, PD, DI,
    Clock, MemCycle, InsCycle, Reset, PACntrl, BMARRegCntrl, BrptRegCntrl, iMMR,
    MPNMC, CNF, RAM, BRAF, SetBRAF, ClrBRAF, iTBLW, DMAMode,
    PrProgValid, DpProgValid, SpProgValid, ExProgValid,
    SpRdWrDet, IFnEx,
    ProgAddr, DataWrite, PrDpReq, PrSpReq, PrPrReq, PrExReq,
    PwDpReq, PwSpReq, PwPrReq, PwExReq, ProgValid,
    DataRead, InsFetch, ProgRead, DFC, StackOut, NextBMAR, BMAR,
    DFCProgEnab, StackDataEnab, StackWriteEnab, BMARReadEnab, BMARProgEnab);


// Tri-state bus drivers
m3s009ct U2 (DFC, StackOut, NextBMAR, BMAR,
    DFCProgEnab, StackDataEnab, StackWriteEnab, BMARReadEnab, BMARProgEnab,
    ProgBus, DataBus, DataWrite, DataRead);

endmodule