m3s012ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Single-port Memory Controller
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.101

// Revision history
// V1.101 - 19 November 1996
//          Read, Write and Program address busses.
//          Separate CE, RD, WR signals for each block.
//          Writes delayed by one cycle.
//          Data read extended to the end of the cycle.
// V1.100 - 22 October 1996
//          PACntrl14 delayed by one cycle.

// m3s012ct
// M320C50 Internal single-port memory controller.
// Provides address and control signals for the internal single-port memory.
// Memory accesses can be extended by driving the SRdy input low.
// If program writes, program reads, data writes, or data reads want to access the same block
// of memory then the accesses are done sequentially in the following order:
// data/program writes, then data reads, then program reads.

`include "m320c50.inc"
`define C_STARTADDR 5'b00010   // Start address of memory in data space bits 14:10


module m3s012ct (ProgAddr, WriteAddr, ReadAddr, 
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    PrRdReq, PrWrReq, DaWrReq, DaRdReq, SRdy,
    MemCycle, FClock, Clock, Reset, MemAccEnab, PACntrl14,
    SARA, SAWA, SAPA, SRNW, SPND, NSCE, NSWE, NSOE,
    WriteReady, SpPmRdy, SpDmRdy,
    SpDataValid, SpProgValid, SpWrRdy, SpDaRdWrDet, SpPrRdWrDet);

    input  [14:0] ProgAddr, WriteAddr, ReadAddr;
    input         PrRdReq, PrWrReq, DaWrReq, DaRdReq, SRdy, WriteReady;
    input         MemCycle, FClock, Clock, Reset, MemAccEnab, PACntrl14;
    output [14:0] SARA, SAWA, SAPA;
    output [`C_NOSB-1:0] SRNW, SPND, NSCE, NSWE, NSOE;
    output        SpPmRdy, SpDmRdy, SpWrRdy;
    output        SpDataValid, SpProgValid;
    output        SpDaRdWrDet, SpPrRdWrDet;

    reg [14:0]        SARA, SAWA, SAPA, DaWrAddr;
    reg [`C_NOSB-1:0] SRNW, SPND, NSCE, NSWE, NSOE;
    reg               SpPmRdy, SpDmRdy, SpWrRdy;
    reg               SpDataValid, SpProgValid;
    reg               WrCycle, PrRdCycle;
    reg               WrActive, PrRdActive, DaRdActive;
    reg [15:0]        WrDecode, PrRdDecode, DaRdDecode;
    reg               DaRdCycRdy, PrRdCycRdy;
    reg               DaRdConflict, PrRdConflict;
    reg               PACntrl14Del, PrWrReqDel, DaWrReqDel;
    reg               DaAddrCmp, PrAddrCmp, SpDaRdWrDet, SpPrRdWrDet;

    integer n;

// Block decoder.
// 4-bit input is extracted from upper address lines using
// the single-port start address and block size constants.
function [`C_NOSB-1:0] BlockDecode;
    input [4:0] Addr;
    reg [3:0] BlockAddr;
    integer n;
begin
    case (`C_SBS)
        0: BlockAddr = Addr[3:0];
        1: BlockAddr = Addr[3:0];
        2: BlockAddr = Addr[4:1];
        3: BlockAddr = {1'b0,Addr[4:2]};
        4: BlockAddr = {2'b0,Addr[4:3]};
        5: BlockAddr = {3'b0,Addr[4]};
        default: BlockAddr = 4'b0;
    endcase
    for (n=0;n<`C_NOSB;n=n+1)
        if (BlockAddr == n) BlockDecode[n] = 1;
        else BlockDecode[n] = 0;
end
endfunction

// Subtract start address from address busses
always @(ReadAddr)  SARA = {ReadAddr[14:10] - `C_STARTADDR,ReadAddr[9:0]};
always @(WriteAddr) DaWrAddr = {WriteAddr[14:10] - `C_STARTADDR,WriteAddr[9:0]};
always @(ProgAddr)  SAPA = {ProgAddr[14:10] - `C_PR,ProgAddr[9:0]};

// Post write address and write requests, combining write addresses
always @(posedge Clock)
    if (MemCycle)
    begin
        if (PrWrReq)
            SAWA <= SAPA;
        else
            SAWA <= DaWrAddr;
        DaWrReqDel <= DaWrReq;
        PrWrReqDel <= PrWrReq;
    end

// Decode write address
always @(SAWA or PrWrReqDel or DaWrReqDel)
    if (PrWrReqDel | DaWrReqDel)
        WrDecode = BlockDecode(SAWA[14:10]);
    else
        WrDecode = 0;

// Decode program read address
always @(SAPA or PrRdReq)
    if (PrRdReq)
        PrRdDecode = BlockDecode(SAPA[14:10]);
    else
        PrRdDecode = 0;

// Decode data read address
always @(SARA or DaRdReq)
    if (DaRdReq)
        DaRdDecode = BlockDecode(SARA[14:10]);
    else
        DaRdDecode = 0;

// Set select lines for read or write
always @(PrRdDecode or DaRdDecode or PrRdActive or DaRdActive)
    for (n=0; n<`C_NOSB; n=n+1)
        SRNW[n] = (PrRdActive & PrRdDecode[n]) | (DaRdActive & DaRdDecode[n]);

// Set select lines for program or data access
always @(DaWrReqDel or WrActive or WrDecode or DaRdActive or DaRdDecode)
    for (n=0;n<`C_NOSB;n=n+1)
        SPND[n] = ~((DaWrReqDel & WrActive & WrDecode[n]) | (DaRdActive & DaRdDecode[n]));

// Ready output signals
always @(SRdy or DaRdReq or DaWrReqDel or PrRdReq or PrWrReqDel
    or WrActive or DaRdConflict or PrRdConflict)
begin
   SpDmRdy = ~(((DaRdReq | DaWrReqDel) & ~SRdy) | DaRdConflict);
   SpPmRdy = ~(((PrRdReq | PrWrReqDel) & ~SRdy) | PrRdConflict);
   SpWrRdy = ~WrActive | SRdy;
end

// Read data valid signal
always @(DaRdActive or WriteReady)
    SpDataValid = DaRdActive & WriteReady;

// Delay PACntrl14
always @(posedge Clock)
   if (MemCycle)
      PACntrl14Del <= PACntrl14;

// Read program valid signal
always @(PrRdActive or WriteReady or PACntrl14Del)
    SpProgValid = PrRdActive & (WriteReady | ~PACntrl14Del);

// Cycle controller
always @(SRdy or WrActive or DaRdActive or
      WrDecode or DaRdDecode or PrRdDecode or WriteReady)
begin
    DaRdConflict = (WrActive && (DaRdDecode & WrDecode));
    PrRdConflict = ((WrActive && (PrRdDecode & WrDecode)) |
                    (DaRdActive && (PrRdDecode & DaRdDecode)));
    DaRdCycRdy = ~(~SRdy | ~WriteReady | DaRdConflict);
    PrRdCycRdy = ~(~SRdy | ~WriteReady | PrRdConflict);
end
     
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        WrCycle <= 0;
        PrRdCycle <= 0;
    end
    else
    begin
        WrCycle <= MemCycle | (WrCycle & ~SRdy);
        PrRdCycle <= MemCycle | (PrRdCycle & ~PrRdCycRdy);
    end

// Access control
always @(DaWrReqDel or PrWrReqDel or WrCycle)
    WrActive = (DaWrReqDel | PrWrReqDel) & WrCycle;
always @(DaRdReq or DaRdConflict)
    DaRdActive = DaRdReq  & ~DaRdConflict;
always @(PrRdReq or PrRdCycle or PrRdConflict)
    PrRdActive = PrRdReq & PrRdCycle & ~PrRdConflict;

// Block enables
always @(WrDecode or PrRdDecode or DaRdDecode or
          WrActive or PrRdActive or DaRdActive or MemAccEnab)
    for (n=0;n<`C_NOSB;n=n+1)
        NSCE[n] = ~(((WrDecode[n] & WrActive)
                   | (PrRdDecode[n] & PrRdActive)
                   | (DaRdDecode[n] & DaRdActive)) & MemAccEnab);

// Read signals
always @(posedge FClock or posedge Reset)
    if (Reset)
        NSOE <= {`C_NOSB{1'b1}};
    else
        for (n=0;n<`C_NOSB;n=n+1)
            NSOE[n] <= ~(((PrRdActive & PrRdDecode[n]) | (DaRdActive & DaRdDecode[n]))
                       & (Clock | ~SRdy) & MemAccEnab);

// Write signals
always @(posedge FClock or posedge Reset)
    if (Reset)
        NSWE <= {`C_NOSB{1'b1}};
    else
        for (n=0;n<`C_NOSB;n=n+1)
            NSWE[n] <= ~ (WrActive & WrDecode[n] & (Clock | ~SRdy) & MemAccEnab);

// Compare read and write address
always @(DaWrAddr or SARA or SAPA)
begin
    if (SARA == DaWrAddr)
        DaAddrCmp = 1;
    else
        DaAddrCmp = 0;
    if (SAPA == DaWrAddr)
        PrAddrCmp = 1;
    else
        PrAddrCmp = 0;
end

// Detect simultaneous read and write to the same address
always @(DaWrReq or PrWrReq or DaRdReq or DaAddrCmp)
    SpDaRdWrDet = DaAddrCmp & (DaWrReq | PrWrReq)  & DaRdReq;
always @(DaWrReq or PrWrReq or PrRdReq or PrAddrCmp)
    SpPrRdWrDet = PrAddrCmp & (DaWrReq | PrWrReq)  & PrRdReq;


endmodule