📄 m3s086ct.v
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//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra //// Auxillary Register Update Controls// Copyright Mentor Graphics Corporation and licensors 1998.// V1.001// Revision history// V1.001 - 30 September 1996// OpCntrlReg[0] used to enable decoding of LST instruction// in generation of IndStall.// V1.000 - 26 February 1996// m3s086ct// M320C50 auxillary register update controls and Source RPTCZero.module m3s086ct (LdRPTCDat, LdRPTCPrg, LdRPTCEx, LdRPTCReg, RPTCZero,//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra // CycCntrlReg, Stall, PACntrl9, RPTStall, ALUCntrlReg11, NormEnab, NormAREnab, InsCycle, OpCntrlReg18, OpCntrlReg22, NLoSStall, DFCAuxStallReg, OpCntrlReg14, LdSTStall, IOins, MMRins, OpRegHi, OpCntrlReg0, RPTC, DataLatch, DataImm, ExecuteReg, DataBus, IndCntrlReg, IndpCntrlReg, IndsCntrlReg, SourceRPTCZero, DAAuxUpdate); input LdRPTCDat, LdRPTCPrg, LdRPTCEx, LdRPTCReg, RPTCZero; input CycCntrlReg, Stall, PACntrl9, RPTStall; input ALUCntrlReg11, NormEnab, NormAREnab, InsCycle; input OpCntrlReg18, OpCntrlReg22, NLoSStall, DFCAuxStallReg; input OpCntrlReg14, LdSTStall, IOins, MMRins, OpCntrlReg0; input [15:0] RPTC, DataLatch, DataImm, ExecuteReg, DataBus; input [6:0] OpRegHi; input [8:0] IndCntrlReg, IndpCntrlReg, IndsCntrlReg; output SourceRPTCZero; output [8:0] DAAuxUpdate; reg SourceRPTCZero; reg [8:0] DAAuxUpdate; reg [15:0] LoadRPTCVal; reg LdRPTCBus, LdRPTCDec, LdRPTCDef; reg IndStall;// SourceRPTCZeroalways @(LdRPTCDat or LdRPTCPrg or LdRPTCEx or LdRPTCReg or RPTCZero or CycCntrlReg or Stall or PACntrl9 or RPTStall or RPTC or DataLatch or DataImm or ExecuteReg or DataBus)begin LdRPTCBus = LdRPTCDat | LdRPTCPrg | LdRPTCEx | LdRPTCReg; LdRPTCDec = (~RPTCZero & ~CycCntrlReg & ~Stall & ~PACntrl9 & ~LdRPTCBus); LdRPTCDef = ~(LdRPTCBus | LdRPTCDec); LoadRPTCVal = (DataLatch & {16{LdRPTCDat}}) | (DataImm & {16{LdRPTCPrg}}) | (ExecuteReg & {16{LdRPTCEx}}) | (DataBus & {16{LdRPTCReg}}); SourceRPTCZero = (LdRPTCBus && !LoadRPTCVal) | (LdRPTCDec && (!RPTC[15:1]) && RPTC[0]) | (LdRPTCDef && !RPTC) | RPTStall;end// Auxillary update controlsalways @(ALUCntrlReg11 or NormEnab or NormAREnab or InsCycle or OpCntrlReg18 or OpCntrlReg22 or NLoSStall or DFCAuxStallReg or OpCntrlReg14 or LdSTStall or IOins or MMRins or CycCntrlReg or OpRegHi or RPTCZero or SourceRPTCZero or Stall or ExecuteReg or IndCntrlReg or IndpCntrlReg or IndsCntrlReg or OpCntrlReg0)begin IndStall = Stall | OpCntrlReg14 | (~OpRegHi[6] & ~OpRegHi[5] & ~OpRegHi[4] & ~OpRegHi[3] & OpRegHi[2] & OpRegHi[1] & OpRegHi[0] & ~LdSTStall & RPTCZero & OpCntrlReg0); if (ALUCntrlReg11) DAAuxUpdate = {1'b0, ExecuteReg[6] | ExecuteReg[5] | ExecuteReg[4], ExecuteReg[6], ExecuteReg[6] & ~(ExecuteReg[5] ^ ExecuteReg[4]), ~ExecuteReg[5], 2'b0, ExecuteReg[3], NormEnab | NormAREnab}; else if (((SourceRPTCZero & RPTCZero) | ((OpCntrlReg18 | OpCntrlReg22) & InsCycle)) & NLoSStall) begin if (DFCAuxStallReg) DAAuxUpdate = IndpCntrlReg; else if (IndStall) DAAuxUpdate = {IndCntrlReg[8:2],2'b0}; else DAAuxUpdate = IndCntrlReg; end else if (((IOins | MMRins) & ~RPTCZero) | (SourceRPTCZero & NLoSStall)) DAAuxUpdate = {IndsCntrlReg[8:2],(IndsCntrlReg[1:0] & {2{~CycCntrlReg}})}; else DAAuxUpdate = IndpCntrlReg;endendmodule⌨️ 快捷键说明
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