📄 m3s030ct.v
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//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra //// TDM Serial Port Receiver// Copyright Mentor Graphics Corporation and Licensors 1998. // V1.009// m3s030ct// M320C50 TDM serial port receiver.// TDR is the input data// FSXI and FSXO are the Frame Synchronisation signals for receive operation.// TDM, FO, FSM are control signals from the TSPC register.// RxSRFull is the receive shift register overflow signal// RxRdy is the receive ready flag// TRNT is the receive interrupt// State machine definitions SPC mode`define C_SPCV_E_RSR_E 0`define C_SPCV_F_RSR_E 1`define C_SPCV_E_RSR_F 2`define C_SPCV_F_RSR_F 3// State machine definitions TDM mode`define C_TDMV_E_RSR_E 4`define C_TDMV_F_RSR_E 5`define C_TDMV_E_RSR_F 6`define C_TDMV_F_RSR_F 7//// TDM Mode operation//// In TDM mode RX shift register is always active,// Only if TDM address matches is the shift register// transfered to the output buffer.//module m3s030ct (Clock, RxClock, NRxClock, RxReset, TxClock, MMRWriteData, WriteTRCV,//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra // ReadTRCV, TDR, FSR, TDM, FO, FSM, RxSRFull, RxRdy, TDMRxValid, RxCount, NextTRCV, TRNT, RxSlot); input [15:0] MMRWriteData; input Clock, RxClock, NRxClock, RxReset, TxClock, WriteTRCV, ReadTRCV; input TDR, FSR, TDM, FO, FSM, TDMRxValid; output [3:0] RxCount; output [15:0] NextTRCV; output RxSRFull, TRNT, RxRdy; output [2:0] RxSlot; reg [15:0] TRCV, NextTRCV, RSR, TRSR; reg RxSRFull, SetSRFullFlag, SetSRFull1, SetSRFull2; reg [3:0] RxCount; // receive bit counter reg TRNT, RxRdy, RxRdyReg, ClrRxRdy; reg RdTRCVSync, RdTRCVTemp; // TRCV read strobe sync latches reg LdTRCVSync, LdTRCV1, LdTRCV2; // TRCV load strobe sync latches reg FSRSync, RxFrame, NextRxFrame; reg [2:0] RxState; reg LastBit, TDMLastBit; reg [2:0] RxSlot, NextRxSlot;// // TRCV register//always @(MMRWriteData or WriteTRCV or LdTRCVSync or TDM or TRSR or RSR or TRCV)begin if (WriteTRCV) NextTRCV = MMRWriteData; else if (LdTRCVSync) begin if (TDM) NextTRCV = TRSR; else NextTRCV = RSR; end else NextTRCV = TRCV;end//// generate receive interrupt on load TRCV//always @(posedge Clock)begin TRCV <= NextTRCV; TRNT <= LastBit;end// Latch ReadTRCV until RdTRCVSync has gone highalways @(posedge Clock) RdTRCVTemp <= (ReadTRCV | (RdTRCVTemp & ~RdTRCVSync)) & RxReset;// Generate RdTRCVSync signal, synchronised to RxClockalways @(posedge RxClock or negedge RxReset)begin if (~RxReset) RdTRCVSync <= 0; else RdTRCVSync <= RdTRCVTemp;end//// receive control state machine//always @(posedge NRxClock or negedge RxReset) // negedge because RxRdy changes on thisbegin if (~RxReset) RxState <= 3'b0; // reset state else case (RxState) `C_SPCV_E_RSR_E: if (LastBit & ~TDM) RxState <= `C_SPCV_E_RSR_F; // frame fills RSR else if (LastBit & TDMRxValid) RxState <= `C_TDMV_E_RSR_F; // TDM mode `C_SPCV_F_RSR_E: if (LastBit & ~RdTRCVSync) RxState <= `C_SPCV_F_RSR_F; // about to overrun else if (LastBit & RdTRCVSync) RxState <= `C_SPCV_E_RSR_F; // read just in time! else if (RdTRCVSync) RxState <= `C_SPCV_E_RSR_E; // read in advance `C_SPCV_E_RSR_F: RxState <= `C_SPCV_F_RSR_E; // always fill TRCV in this case `C_SPCV_F_RSR_F: if (RdTRCVSync) RxState <= `C_SPCV_E_RSR_F; // either get a read or overrun `C_TDMV_E_RSR_E: if (LastBit & TDMRxValid) RxState <= `C_TDMV_E_RSR_F; `C_TDMV_F_RSR_E: if (LastBit & TDMRxValid & RdTRCVSync) RxState <= `C_TDMV_E_RSR_F; else if (LastBit & TDMRxValid & ~RdTRCVSync) RxState <= `C_TDMV_F_RSR_F; else if (RdTRCVSync) RxState <= `C_TDMV_E_RSR_E; `C_TDMV_E_RSR_F: RxState <= `C_TDMV_F_RSR_E; `C_TDMV_F_RSR_F: RxState <= `C_TDMV_F_RSR_E; default: RxState <= RxState; // there isn't one but for safety endcaseend//// LastBit signal//always @(RxCount or RxFrame or TDM or TDMLastBit) LastBit = (((RxCount == 15) && (RxFrame & ~TDM)) | TDMLastBit);always @(posedge RxClock or negedge RxReset) if (~RxReset) TDMLastBit <= 0; else TDMLastBit <= ((RxCount == 15) && TDMRxValid);// Generate SetSRFullFLag, synchronised to -ve edge of RXClockalways @(posedge NRxClock or negedge RxReset) if (~RxReset) SetSRFullFlag <= 0; else SetSRFullFlag <= (RxState == `C_SPCV_F_RSR_F) && (~FSM | FSR);// RxSRFull flag re-synchronised to Clockalways @(posedge Clock or negedge RxReset) if (~RxReset) begin SetSRFull1 <= 0; SetSRFull2 <= 0; RxSRFull <= 0; end else begin SetSRFull1 <= SetSRFullFlag; SetSRFull2 <= SetSRFull1; RxSRFull <= ((SetSRFull1 & ~SetSRFull2) | RxSRFull) & ~ReadTRCV; end//// Receive counter - counts 0,1,2,3,4,5,14,15 if FO == 1, 0 to 15 if FO == 0//always @(posedge NRxClock or negedge RxReset)begin if (~RxReset) RxCount <= 4'b1110 ; // note below that RxSRFull will abort the receive else if (FSRSync & (~RxSRFull | TDM)) RxCount <= 4'b0 ; else if (FO & (RxCount == 5)) RxCount <= 14; else RxCount <= RxCount + 1;end//// TDM Slot counter//always @(posedge NRxClock or negedge RxReset)begin if (~RxReset) RxSlot <= 0; else if (FSRSync) RxSlot <= 0; else if (RxCount == 15) RxSlot <= NextRxSlot;end//always @(RxSlot)begin NextRxSlot = RxSlot + 1;end//// Receiving frame flag//always @(RxReset or FSRSync or RxSRFull or LastBit or FSM or RxState or RxFrame or TDM)begin if ((FSRSync & ~RxSRFull) | TDM) NextRxFrame = 1; else if (LastBit & (FSM | (RxSRFull && (RxState == `C_SPCV_F_RSR_F)))) NextRxFrame = 0; else NextRxFrame = RxFrame;endalways @(posedge NRxClock or negedge RxReset)begin if (~RxReset) RxFrame <= 0; else RxFrame <= NextRxFrame;end//// Frame Sync control synchronisation//always @(posedge NRxClock or negedge RxReset)begin if (~RxReset) FSRSync <= 0; else FSRSync <= FSR;end//// RSR = receive shift register//always @(posedge TxClock)begin TRSR <= {TRSR[14:0],(TDR & TDM)}; // TDM, sample on posedge of clockendalways @(posedge NRxClock)begin if (NextRxFrame) begin RSR <= {RSR[14:0],(TDR & ~TDM)}; endend//// sychronise load signal to Clock//always @(posedge Clock)begin LdTRCV1 <= LastBit; LdTRCV2 <= LdTRCV1;endalways @(LdTRCV1 or LdTRCV2)begin LdTRCVSync = LdTRCV1 & ~LdTRCV2;end//// generate RxRdy clear signal//always @(posedge Clock or negedge RxReset)begin if (~RxReset) ClrRxRdy <= 0; else ClrRxRdy <= ReadTRCV | (ClrRxRdy & RxRdyReg);end//// generate RxRdy signal//always @(posedge NRxClock or negedge RxReset)begin if (~RxReset) RxRdyReg <= 0; else RxRdyReg <= ((TDMRxValid | ~TDM) & LastBit) | (RxRdyReg & ~ClrRxRdy);endalways @(RxRdyReg or ClrRxRdy or ReadTRCV)begin RxRdy = RxRdyReg & ~(ClrRxRdy | ReadTRCV);endendmodule⌨️ 快捷键说明
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