m3s017ct.v

这是16位定点dsp源代码。已仿真和综合过了

        else PSHDDec = 0;
        if (OpReg[15:0] == 16'hBE32) iPOPDec = 1;
        else iPOPDec = 0;
        if (OpReg[15:8] == 8'h8A) POPDDec = 1;
        else POPDDec = 0;
        if (OpReg == 16'hBEC6) RPTBDec = 1;
        else RPTBDec = 0;
    end
    else
    begin
        iPUSHDec = 0;
        PSHDDec = 0;
        iPOPDec = 0;
        POPDDec = 0;
        RPTBDec = 0;
    end
    StackSelDec[0] = ~(OpCntrlReg[12] | iPUSHDec);
    StackSelDec[1] = iPUSHDec | PSHDDec;
    StackSelDec[2] = IntrOp & ~DelIntrPush;
    PushDec = ((OpCntrlReg[10] | OpCntrlReg[8] | OpCntrlReg[7] | OpCntrlReg[6])
               & BANZEnable)
              | iPUSHDec | PSHDDec;
    PopDec = (OpCntrlReg[2] & OpCntrlReg[0] & BANZEnable) | iPOPDec | POPDDec;
end

// Data read control decode
always @(InstructReg or FCycDec or EnableDec or LARDec or iLARd or iLARsi or iLARli
     or OpCntrlReg or OpReg or ExCntrlReg)
begin
    if (FCycDec)
    begin
        ReadDec = ~(iLARsi | iLARli);
        RdIndirDec = (iLARd & InstructReg[7]) | (((OpCntrlReg[22] & ~OpReg[15]) | OpCntrlReg[18]) & OpReg[7]);
        RdImmDec = ~LARDec & ~ExCntrlReg[8] & ~((OpCntrlReg[18] | OpCntrlReg[22]) & ~OpReg[15]);
        RdSupDPDec = OpCntrlReg[22] & ~OpReg[15];
    end
    else
    begin
        if (EnableDec)
        begin
            ReadDec = (~InstructReg[15] & (~InstructReg[14] | ~InstructReg[13] | ~InstructReg[12] | ~InstructReg[11])
                & ~(~InstructReg[14] & ~InstructReg[13] & ~InstructReg[12] & InstructReg[11] & ~InstructReg[9] &
                   ((~InstructReg[10] & InstructReg[8]) | (InstructReg[10] & ~InstructReg[8]))))
                | (InstructReg[15] & ~InstructReg[14] & InstructReg[13] & ~InstructReg[12] & ~InstructReg[10] & InstructReg[9]);
            RdIndirDec = InstructReg[7];
            RdImmDec = 0;
            RdSupDPDec = ~InstructReg[15] & ~InstructReg[14] & ~InstructReg[13] & ~InstructReg[12] &
                InstructReg[11] & ~InstructReg[10] & ~InstructReg[9] & ~InstructReg[8];
        end
        else
        begin
            ReadDec = OpCntrlReg[18];
            RdIndirDec = OpReg[7];
            RdImmDec = OpCntrlReg[18] & OpReg[15];
            RdSupDPDec = 0;
        end
    end
end

always @(ReadDec or RdIndirDec or RdImmDec or RdSupDPDec or InsCycle
     or LoadPipe or DRCntrlReg or DRpCntrlReg or BCRStall or iLARd or LARStallDec
     or ExCntrlReg)
begin
    if ((InsCycle | (BCRStall & ~(iLARd | LARStallDec | ExCntrlReg[5]))) & LoadPipe)
    begin
        DRCntrlRegDec = {RdSupDPDec,RdImmDec,RdIndirDec,ReadDec};
        DRpCntrlRegDec = DRCntrlReg;
    end
    else
    begin
        DRCntrlRegDec = DRCntrlReg;
        DRpCntrlRegDec = DRpCntrlReg;
    end
end

// Data write control decode
always @(OpReg or OpCntrlReg or POPDDec or ExCntrlReg
    or InsCycle or LoadPipe or DWCntrlReg)
begin
    if (OpCntrlReg[0])
    begin
        WriteDec = OpCntrlReg[5] | POPDDec;
        WrIndirDec = OpReg[7];
        WrImmDec = OpCntrlReg[15];
        if ((OpReg[15:8] == 8'h88) || ((OpReg[15:9] == 7'b1000111) & ~OpReg[7]))
            WrSupDPDec = 1;
        else WrSupDPDec = 0;
        if ((OpReg[15:8] == 8'h77) || (OpReg[15:8] == 8'h72)
           || ((OpReg[15:12] == 4'hA) && (OpReg[10:8] == 3'b011)))
           WrDMOVDec = 1;
        else WrDMOVDec = 0;
    end
    else
    begin
        WriteDec = 0;
        WrIndirDec = 0;
        WrImmDec = 0;
        WrSupDPDec = 0;
        WrDMOVDec = 0;
    end
    if (InsCycle & LoadPipe)
        DWCntrlRegDec = {WrDMOVDec,WrSupDPDec,WrImmDec,WrIndirDec,WriteDec};
    else
        DWCntrlRegDec = DWCntrlReg;
end

// Aux register control decode
always @(OpCntrlReg or OpReg or LARCntrlReg)
    if (OpCntrlReg[0])
    begin
        if (OpReg[15:8] == 8'h0E) LdST0Dec = 1;
        else LdST0Dec = 0;
        if (OpReg[15:8] == 8'h0F) LdST1Dec = 1;
        else LdST1Dec = 0;
        if (OpReg[15:8] == 8'h8E) RdST0Dec = 1;
        else RdST0Dec = 0;
        if (OpReg[15:8] == 8'h8F) RdST1Dec = 1;
        else RdST1Dec = 0;
        if (LARCntrlReg[0]) LARdDec = 1;
        else LARdDec = 0;
        if (LARCntrlReg[2] | LARCntrlReg[1]) LARpDec = 1;
        else LARpDec = 0;
    end
    else
    begin
        LdST0Dec = 0;
        LdST1Dec = 0;
        RdST0Dec = 0;
        RdST1Dec = 0;
        LARdDec = 0;
        LARpDec = 0;
    end

// Load control decode
always @(OpReg or OpCntrlReg)
    if (OpCntrlReg[0])
    begin
        // Load DP
        if (OpReg[15:8] == 8'h0D) LdDPDatDec = 1;
        else LdDPDatDec = 0;
        if (OpReg[15:9] == 7'b1011110) LdDPPrgDec = 1;
        else LdDPPrgDec = 0;
    end
    else
    begin
        LdDPDatDec = 0;
        LdDPPrgDec = 0;
   end

// CALU control decode
always @(OpReg or OpCntrlReg or ALUNormDec or ALUSubCDec or iPUSHDec or iPOPDec
      or SRSATHDec or SRSATLDec)
begin
    if (OpReg[15:7] == 9'b101111111) PreShftLow = 1;
        else PreShftLow = 0;
    if ((OpReg[14:12] == 3'b001) || (OpReg[15:13] == 3'b001)
       || (OpReg[15:12] == 4'h4))
        PreShftHigh = 1;
        else PreShftHigh = 0;
    if (OpCntrlReg[0])
    begin
        if ((OpReg[15:12] == 4'hA) && (OpReg[10:9] == 2'b01))
            Macs = 1;
        else Macs = 0;
        if (OpReg[15:8] == 8'h55) iMPYU = 1;
        else iMPYU = 0;
        if (((OpReg[15:6] == 10'b1011111010) & (OpReg[1] | OpReg[0])) ||
           ((OpReg[15:12] == 4'h6) &&
           ((OpReg[11:8] == 4'h1) || (OpReg[11:8] == 4'h5) ||
            (OpReg[11:8] == 4'h8) || (OpReg[11:8] == 4'hA))))
            PreSL16Dec = 1;
        else PreSL16Dec = 0;
        if (OpReg[15:8] == 8'h68) PreZALRDec = 1;
            else PreZALRDec = 0;
        if ((OpReg[15:8] == 8'hBE) && ((OpReg[7:0] == 8'h59) || (OpReg[7:0] == 8'hC5)))
            ClrAccDec = 1;
        else ClrAccDec = 0;
        if ((OpReg[15:8] == 8'hBE) && ((OpReg[7:1] == 7'b0101100) || (OpReg[7:0] == 8'hC5)))
            ClrPRegDec = 1;
        else ClrPRegDec = 0;
        if (((OpReg[15:12] == 4'h6) && ((OpReg[11] & OpReg[10]) || 
              (~OpReg[11] & ~OpReg[8]) || (OpReg[11] & ~OpReg[9])))
            || (OpReg[15:8] == 16'h08) || iPOPDec || ALUSubCDec
            || ((OpReg[15:8] == 16'hBF) && ((OpReg[7:4] == 4'hB)||(OpReg[7:6] == 2'b11))))
            PreSuppDec = 1;
        else PreSuppDec = 0;
        if (((OpReg[15:12] == 4'h7) && ((OpReg[11:10] == 2'b00) || (OpReg[11:8] == 4'h4)))
           || (OpReg[15:9] == 7'b0101001) | Macs)
            LdTRDec = 1;
        else LdTRDec = 0;
        if (PreShftLow || (PreShftHigh && (OpReg[15:14] == 2'b00)) || PreSL16Dec || ALUSubCDec ||
           (OpReg[15:8] == 8'h08) || ((OpReg[15:12] == 4'h6) && (OpReg[11:8] != 4'hF)) ||
           ((OpReg[15:11] == 5'b10111) && !OpReg[10] && !(OpReg[9] & OpReg[8])) ||
           ((OpReg[15:8] == 8'hBE) && (OpReg[7:5] == 3'h0) && (OpReg[3:0] != 4'hE)) ||
           ((OpReg[15:12] == 4'h7) && (((OpReg[11:10] == 2'b00) && (OpReg[9:8] != 2'b11)) || (OpReg[11:8] == 4'h4))) ||
            (OpReg[15:10] == 6'b010100) || Macs || ALUNormDec || ClrAccDec || iPOPDec ||
            SRSATHDec || SRSATLDec)
            LdAccDec = 1;
        else LdAccDec = 0;
        if ((OpReg[15:4] == 12'hBE1) && ((OpReg[3:2] == 2'b01) ||
                   (OpReg[3:1] == 3'b110) || (OpReg[3:0] == 4'hB) || (OpReg[3:0] == 4'hE)))
            LdAccBDec = 1;
        else LdAccBDec = 0;
        if (((OpReg[15:12] == 4'h5) && ((OpReg[11:10] == 2'b00) || (OpReg[11:9] == 3'b010)))
           || (OpReg[15:13] == 3'b110) || (OpReg == 16'hBE80) | Macs)
            LdPDec = 1;
        else LdPDec = 0;
        if (OpReg[15:8] == 8'h75) LPHDec = 1;
        else LPHDec = 0;
        if ((OpReg[15:12] == 4'h9) || (OpReg[15:8] == 8'h88) || OpCntrlReg[11] ||
           iPUSHDec)
            StAccDec = 1;
        else StAccDec = 0;
        if (OpReg[15:8] == 8'h8C) SPLDec = 1;
        else SPLDec = 0;
        if (OpReg[15:8] == 8'h8D) SPHDec = 1;
        else SPHDec = 0;
        if (OpReg[15:8] == 8'h8E) ST0Dec = 1;
        else ST0Dec = 0;
        if (OpReg[15:8] == 8'h8F) ST1Dec = 1;
        else ST1Dec = 0;
        if (((OpReg[15:12] == 4'h6) && (OpReg[9:8] == 2'b11) &&
           ((OpReg[11] == 1'b0) || (OpReg[10] == 1'b0))) | SRSATHDec | SRSATLDec)
            PreTR1Dec = 1;
        else PreTR1Dec = 0;
        if (OpReg[15:8] == 8'h6F) PreTR2Dec = 1;
        else PreTR2Dec = 0;
        PreEnab = PreShftHigh | PreShftLow | PreTR1Dec | PreTR2Dec |
            ((OpReg[15:12] == 4'hB) & ((OpReg[11:7] == 5'b11110)|!OpReg[11]));
        if (((OpReg[15:10] == 6'b101111) & ~iPOPDec) || Macs)
            CALUSrcDec = 1;
        else CALUSrcDec = 0;
        if (PreEnab | OpCntrlReg[14])
        begin
            if (!OpReg[15] || (OpReg[15:13] == 3'b100) || (OpReg[15:11] == 5'b10110))
                ShiftDec = OpReg[11:8];
            else
                ShiftDec = OpReg[3:0];
        end
        else if (ALUSubCDec) ShiftDec = 4'hF;
        else ShiftDec = 4'h0;
        if ((OpReg[15:4] == 12'hBF0) && (OpReg[3:2] == 2'b0))
            LdPMDec = 1;
        else LdPMDec = 0;
        if ((OpReg[15:8] == 8'h6F) || (OpReg[15:12] == 4'h4)) BitTestEnabDec = 1;
        else BitTestEnabDec = 0;
    end
    else
    begin
        LdTRDec = 0;
        LdAccDec = 0;
        StAccDec = 0;
        LdPDec = 0;
        LPHDec = 0;
        ST0Dec = 0;
        ST1Dec = 0;
        SPLDec = 0;
        SPHDec = 0;
        CALUSrcDec = 0;
        PreTR1Dec = 0;
        PreTR2Dec = 0;
        PreSL16Dec = 0;
        PreEnab = 0;
        ShiftDec = 0;
        LdAccBDec = 0;
        PreZALRDec = 0;
        PreSuppDec = 0;
        ClrAccDec = 0;
        ClrPRegDec = 0;
        LdPMDec = 0;
        Macs = 0;
        iMPYU = 0;
        BitTestEnabDec = 0;
    end
end

// ALU control decode
always @(OpReg or OpCntrlReg or Macs)
    if (OpCntrlReg[0])
    begin
        if ((OpReg == 16'hBE11) || (OpReg[15:8] == 8'h60) ||
            (OpReg == 16'hBE19) || (OpReg[15:8] == 8'h64))
            ALUCEnabDec = 1;
        else ALUCEnabDec = 0;
        if (((OpReg[15:4] == 12'hBE0) && ((OpReg[3:0] == 4'h3) || (OpReg[3:2] == 2'b01)))
           || (OpReg[15:11] == 5'b01110) || (OpReg[15:10] == 6'b010100) || Macs)
           ALUSrcPRegDec = 1;
        else ALUSrcPRegDec = 0;
        if (OpReg[15:4] == 12'hBE1) ALUSrcAccBDec = 1;
        else ALUSrcAccBDec = 0;
        if (OpReg == 16'hBE02) ALUNegDec = 1;
        else ALUNegDec = 0;
        if (OpReg == 16'hBE00) ALUAbsDec = 1;
        else ALUAbsDec = 0;
        if (OpReg[15:8] == 8'h0A) ALUSubCDec = 1;
        else ALUSubCDec = 0;
        if (OpReg == 16'hBE1B) ALUCrGtDec = 1;
        else ALUCrGtDec = 0;
        if (OpReg == 16'hBE1C) ALUCrLtDec = 1;
        else ALUCrLtDec = 0;
        if (OpReg[15:8] == 8'hA0) ALUNormDec = 1;
        else ALUNormDec = 0;

        if ((OpReg[15:8] == 8'h6E) || (OpReg[15:4] == 12'hBFB) ||
           ((OpReg[15:8] == 8'hBE) && ((OpReg[7:0] == 8'h81) || (OpReg[7:0] == 8'h12))))
            ALUFunctionDec = 3'o5; // AND
        else if ((OpReg[15:8] == 8'h6D) || (OpReg[15:4] == 12'hBFC) ||
           ((OpReg[15:8] == 8'hBE) && ((OpReg[7:0] == 8'h82) || (OpReg[7:0] == 8'h13))))
            ALUFunctionDec = 3'o2; // OR
        else if ((OpReg[15:8] == 8'h6C) || (OpReg[15:4] == 12'hBFD) ||
           ((OpReg[15:8] == 8'hBE) && ((OpReg[7:0] == 8'h83) || (OpReg[7:0] == 8'h1A))))
            ALUFunctionDec = 3'o3; // XOR
        else if ((OpReg[15:12] == 4'h2) || (OpReg[15:10] == 6'b011000) ||
           (OpReg[15:8] == 8'hB8) || (OpReg[15:4] == 12'hBF9) ||
           ((OpReg[15:4] == 12'hBE1) && (OpReg[3:1] == 3'b000)) ||
           (OpReg == 16'hBE04) ||
           ((OpReg[15:14] == 2'b01) && (OpReg[12:10] == 3'b100) && ~OpReg[8]) ||
           ((OpReg[15:10] == 6'b010100) & ~OpReg[8]) ||
           ((OpReg[15:12] == 4'hA) && (OpReg[10:9] == 2'b01)) )
            ALUFunctionDec = 3'o4; // ADD
        else if ((OpReg[15:12] == 4'h3) || (OpReg[15:10] == 6'b011001) ||
           (OpReg[15:8] == 8'hBA) || (OpReg[15:4] == 12'hBFA) ||
           ((OpReg[15:4] == 12'hBE1) && (OpReg[3:1] == 3'b100)) ||
           (OpReg[15:8] == 8'h0A) || (OpReg == 16'hBE05) ||
           ((OpReg[15:10] == 6'b010100) && OpReg[8]) || (OpReg[15:8] == 8'h74) ||
           ALUCrGtDec | ALUCrLtDec)
            ALUFunctionDec = 3'o6; // SUB
        else if ((OpReg == 16'hBE01) | ALUNegDec | ALUAbsDec)
            ALUFunctionDec = 3'o1; // NOT
        else ALUFunctionDec = 3'o7;
    end
    else
    begin
        ALUNormDec = 0;
        ALUCrLtDec = 0;
        ALUCrGtDec = 0;
        ALUSubCDec = 0;
        ALUAbsDec = 0;
        ALUNegDec = 0;
        ALUCEnabDec = 0;
        ALUSrcPRegDec = 0;
        ALUSrcAccBDec = 0;
        ALUFunctionDec = 0;
    end

// ALU shift/rotate control decode
always @(OpReg or OpCntrlReg or ALUNormDec)
    if (OpCntrlReg[0])
    begin
        if ((OpReg[15:8] == 8'hBE) &&
            ((OpReg[7:3] == 5'b00001) || (OpReg[7:2] == 6'b000101)))
        begin
            SREnabDec = 1;
            SRLeftDec = ((OpReg[4] & ~OpReg[0]) | (OpReg[3] & (OpReg[2]^OpReg[0])));
            SRRotDec = (OpReg[2] & ~OpReg[1]);
            SRIncBDec = OpReg[4];
        end
        else
        begin
            SREnabDec = ALUNormDec;
            SRLeftDec = 0;
            SRRotDec = 0;
            SRIncBDec = 0;
        end
        if (OpReg[15:4] == 12'hBFE) SRBSARDec = 1;
        else SRBSARDec = 0;
        if (OpReg == 16'hBE5A) SRSATHDec = 1;
        else SRSATHDec = 0;
        if (OpReg == 16'hBE5B) SRSATLDec = 1;
        else SRSATLDec = 0;
    end
    else
    begin
        SREnabDec = 0;
        SRLeftDec = 0;
        SRRotDec = 0;
        SRIncBDec = 0;
        SRBSARDec = 0;
        SRSATHDec = 0;
        SRSATLDec = 0;
    end

// Set/Clear bit control decode
always @(OpCntrlReg or OpReg)
begin
    SetClrDec = OpCntrlReg[0] & (OpReg[15:4] == 12'hBE4);
    ClrcIntmDec = SetClrDec & (OpReg[3:0] == 4'h0);
end
always @(posedge Clock or posedge Reset)
    if (Reset) SetClrCntrl <= 9'b0;
    else if (AdvPipe)
    begin
        if (SetClrDec)
        begin
        case (OpReg[3:1])
            3'o0 : SetClrCntrl[8:1] <= 8'b10000000;
            3'o1 : SetClrCntrl[8:1] <= 8'b00000001;
            3'o2 : SetClrCntrl[8:1] <= 8'b00000010;
            3'o3 : SetClrCntrl[8:1] <= 8'b00000100;
            3'o4 : SetClrCntrl[8:1] <= 8'b01000000;
            3'o5 : SetClrCntrl[8:1] <= 8'b00001000;
            3'o6 : SetClrCntrl[8:1] <= 8'b00010000;
            3'o7 : SetClrCntrl[8:1] <= 8'b00100000;
        endcase
        SetClrCntrl[0] <= OpReg[0];
        end
        else SetClrCntrl <= 9'b0;
    end

endmodule