m3s017ct.v

这是16位定点dsp源代码。已仿真和综合过了

            TableIns <= TableOp & ~TableIns;
            BCRnD <= BCRnDDec;
            XCDel <= XCDis & OpReg[12];
            XCi <= XCDec;
            XC2 <= XCDec & InstructReg[12];
            end
        if (AdvPipe & RPTCZero & ~BlkMovStall)
            LARCntrlReg <= {iLARli,iLARsi,iLARd};
        if (MemCycle & LoadPipe & RPTCZero & ~BlkMovStall)
            LdCntrlReg <= {LdDPPrgDec,LdDPDatDec};
        if (AdvPipe & LoadPipe)
        begin
            TableOp <= TBLWDec | TBLRDec;
            iIdle <= IdleDec & ~InstructReg[0];
            iIdle2 <= IdleDec & InstructReg[0];
            IdleEx <= iIdle | iIdle2;
            PLUCntrlReg <= {OpCntrlReg[4:3],OpReg[10:8]};
            MultCntrl <= iMPYU;
            TestCnd <= TestCndDec;
            BitTestEnab <= BitTestEnabDec;
        end
    end

// Pipeline stall decodes
always @(OpCntrlReg or BlkMovStall or LdDPStall or TBLRStall or InsCycle)
    BlkMovStallDec = (((OpCntrlReg[15] | OpCntrlReg[16]) & InsCycle)
                     & ~(BlkMovStall | LdDPStall)) | TBLRStall;

always @(LdDPDatDec or LdDPPrgDec or LdDPStall or RPTCZero)
    LdDPStallDec = (LdDPDatDec | LdDPPrgDec) & ~LdDPStall & RPTCZero;

always @(LdST0Dec or LdST1Dec or LdSTStall or RPTCZero)
    LdSTStallDec = (LdST0Dec | LdST1Dec) & ~LdSTStall & RPTCZero;

always @(OpReg or OpCntrlReg)
    RPTStallDec = OpCntrlReg[0] & 
        (((OpReg[15:12] == 4'h0) || (OpReg[15:12] == 4'hB)) & (OpReg[11:8] == 4'hB));

always @(LARCntrlReg or RPTCZero or LARStall)
    LARStallDec = (LARCntrlReg[1] | LARCntrlReg[0]) & RPTCZero & ~LARStall;

always @(OpCntrlReg or InsCycle)
    TBLRStallDec = OpCntrlReg[21] & InsCycle;

// Conditional execute pipeline stuffing
always @(XCDel or XCDis or BCRnD or BCREnable)
begin
    XCSkip = XCDis | XCDel;
    BCRSkip = BCRnD & BCREnable;
end

// Determine whether fetched instruction is to be executed
always @(IntrIns or OpCntrlReg or BCRSkip)
    IFDis = IntrIns | BCRSkip |
        OpCntrlReg[2] | OpCntrlReg[6] | OpCntrlReg[7] | OpCntrlReg[8] | OpCntrlReg[11];
always @(IFDis or IFDel)
    IFnEx = IFDis | IFDel;

// BCRX Conditions and auxillary register controls
m3s046ct U2 (NBIO, TC, AccNZ, AccLZ, C, OV,
  InstructReg[15:3], OpReg[9:0], OpReg[11],
  ExecuteReg[9:0], ExecuteReg[13], ExecuteReg[14], ExecuteReg[15],
  OpCntrlReg[0], OpCntrlReg[1], OpCntrlReg[2], OpCntrlReg[6],
  OpCntrlReg[7], OpCntrlReg[8], OpCntrlReg[9], OpCntrlReg[10], OpCntrlReg[12],
  OpCntrlReg[18], OpCntrlReg[22],
  ExCntrlReg[2], ExCntrlReg[3], ExCntrlReg[5], ExCntrlReg[7], ExCntrlReg[8],
  XCDel, BCRnD, IntrIns, ARZ, XCi, MMRins, IOins, RPTCZero, CycCntrlReg,
  BCREnable, XCDis, IndCntrlReg);

// Clear OV flag after testing
always @(TestCnd or ExecuteReg or InsCycle)
    ClrOV = TestCnd & ~ExecuteReg[11] & ~ExecuteReg[10] & ExecuteReg[1] & InsCycle;

// Operand control decode
always @(InstructReg or OpCntrlReg or ExCntrlReg or BANZEnable or BCRDec
    or IntrIns or IntrOp or BCREnable or XCDis or XCSkip or BCRSkip)
begin
    BCRnDDec = BCRDec & ~OpCntrlReg[12];

    // Disable execution
    EnableDec = ~((((ExCntrlReg[3] & ~ExCntrlReg[5]) | ExCntrlReg[2]) &
         ~(IntrIns & ~(ExCntrlReg[8] | ExCntrlReg[7])) & BCREnable) | BCRnDDec)
                & OpCntrlReg[1] & ~(XCSkip | BCRSkip);

    // Branch/Call instructions
    if ((InstructReg[15:11] == 5'b01111) && (InstructReg[9:8] == 2'b01)) iB = 1;
    else iB = 0;
    if ((InstructReg[15:11] == 5'b01111) && (InstructReg[9:8] == 2'b11)) iBANZ = 1;
    else iBANZ = 0;
    if ((InstructReg[15:13] == 3'b111) && (InstructReg[11:10] == 2'b00)) iBCND = 1;
    else iBCND = 0;
    if (InstructReg[15:1] == 15'h5F10) iBACC = 1;
    else iBACC = 0;
    if ((InstructReg[15:11] == 5'b01111) && (InstructReg[9:8] == 2'b10)) iCALL = 1;
    else iCALL = 0;
    if ((InstructReg[15:13] == 3'b111) && (InstructReg[11:10] == 2'b10)) iCC = 1;
    else iCC = 0;
    if ((InstructReg[15:0] == 16'hBE30) || (InstructReg[15:0] == 16'hBE3D)) iCALA = 1;
    else iCALA = 0;

    // Next word is an opcode
    case (InstructReg[15:12])
        4'h0: if ((InstructReg[11:8] == 4'h9) || (InstructReg[11:8] == 4'hC))
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        4'h5: if (InstructReg[11:10] == 2'b11)
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        4'h7: if ((InstructReg[11] == 1) &&
                 ((InstructReg[9:8] == 2'b01) || (InstructReg[9] == 1)))
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        4'h8: if (InstructReg[11:8] == 4'h9)
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        4'hA: if ((InstructReg[11:9] == 3'b001) || (InstructReg[11:8] == 4'h5) ||
                  (InstructReg[11:9] == 3'b100) || (InstructReg[11:9] == 3'b111))
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        4'hB: if (((InstructReg[11:9] == 3'b111) && InstructReg[7] &&
                    (~InstructReg[6] || ~InstructReg[5])) ||
                  ((InstructReg[11:8] == 4'hF) && ~InstructReg[7] && InstructReg[3]))
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        4'hE: if (InstructReg[10] == 1'b0)
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        4'hF: if (InstructReg[10] == 1'b0)
                  OpcodeDec = 0;
              else OpcodeDec = 1;
        default: OpcodeDec = 1;
    endcase

    if (EnableDec) InsDec = OpcodeDec;
    else InsDec = 1;

    if (EnableDec)
    begin

        // Branch instruction
        BrnchDec = iB | iBANZ | iBCND | iBACC;

        // Call instruction
        CallDec = iCALL| iCC | iCALA;

        // Branch/Call Accumulator instruction
        BCAccDec = iBACC | iCALA;

        // Return instruction
        if ((((InstructReg[15:13] == 3'b111) && (InstructReg[11:10] == 2'b11)) ||
            ((InstructReg[15:4] == 12'hBE3) && (InstructReg[3:2] == 2'b10))))
            RetDec = 1;
        else RetDec = 0;

        // Conditional execute instruction
        if ((InstructReg[15:13] == 3'b111) && (InstructReg[11:10] == 2'b01))
            XCDec = 1;
        else XCDec = 0;

        // Interrupt instruction
        if (InstructReg[15:5] == 11'b10111110011)
            IntrDec = 1;
        else
            IntrDec = 0;

        // TRAP instruction
        if ((InstructReg[15:8] == 8'hBE) &&
            ((InstructReg[7:4] == 4'h3) || (InstructReg[7:4] == 4'h5)) &&
             (InstructReg[3:0] == 4'h1))
            TrapDec = 1;
        else
            TrapDec = 0;

        // NMI instruction
        if (InstructReg[15:1] == 15'b101111100101001)
            NMIDec = 1;
        else
            NMIDec = 0;

        // BCR stall instruction
        BCRStallInsDec = (RetDec | IntrDec | TrapDec | NMIDec | iBACC | iCALA) & ~BCRDec;

        // Delayed instruction
        if ((InstructReg[15:10] == 6'b011111) || (InstructReg[15:12] == 4'hF) ||
            (iBACC & InstructReg[0]) || (iCALA & InstructReg[0]) ||
            (iBANZ & InstructReg[10]) || (TrapDec & InstructReg[5]))
            DelDec = 1;
        else
            DelDec = 0;

        // PLU instruction
        if (InstructReg[15:11] == 5'b01011)
            PLULDec = 1;
        else PLULDec = 0;
        if (InstructReg[15:8] == 8'hAE)
            PLUIDec = 1;
        else PLUIDec = 0;

        // LAR instruction
        if (InstructReg[15:11] == 5'b00000) iLARd = 1;
        else iLARd = 0;
        if (InstructReg[15:11] == 5'b10110) iLARsi = 1;
        else iLARsi = 0;
        if (InstructReg[15:3] == 13'b1011111100001) iLARli = 1;
        else iLARli = 0;
        LARDec = iLARd | iLARsi | iLARli;

        // Block move instructions
        if (InstructReg[15:8] == 8'hA6) TBLRDec = 1;
        else TBLRDec = 0;
        if (InstructReg[15:8] == 8'hA7) TBLWDec = 1;
        else TBLWDec = 0;
        if (((InstructReg[15:12] == 4'hA) &&
               ((InstructReg[11:8] == 4'h9) || (InstructReg[11:8] == 4'hD)))
            || TBLWDec)
            DFCDstDec = 1;
        else
            DFCDstDec = 0;
        if ((InstructReg[15:12] == 4'hA) && ((InstructReg[11:9] == 3'b010) ||
               (InstructReg[11:8] == 4'h8) || (InstructReg[11:8] == 4'hC)))
            BlkMovSrcDec = 1;
        else
            BlkMovSrcDec = 0;
        if ((InstructReg[15:12] == 4'hA) && (InstructReg[10:9] == 2'b01))
            MadMacDec = 1;
        else
            MadMacDec = 0;
        if (InstructReg[15:9] == 7'b0101011)
            DPMovDec = 1;
        else
            DPMovDec = 0;

        // I/O instruction
        if ((InstructReg[15:8] == 8'h0C) | (InstructReg[15:8] == 8'hAF))
            IODec = 1;
        else IODec = 0;

        // MMR instruction
        if (InstructReg[14:8] == 7'h09) MMRDec = 1;
        else MMRDec = 0;

        // DFC instruction
        DFCSrcDec = BlkMovSrcDec | MadMacDec | TBLRDec;
        DFCWr = TBLRDec | TBLWDec;
        DFCProg = MMRDec |
                 (DFCSrcDec & ((InstructReg[11:10] == 2'b00) |
                               (InstructReg[10:8] == 3'b101) |
                               (InstructReg[10:8] == 3'b000))) |
                 (DFCDstDec & ~InstructReg[10]);
        DFCReg = (DFCSrcDec | DFCDstDec) & ~(DFCProg | DFCWr);


        // Write instruction
        if (PLUIDec || (PLULDec & (InstructReg[9:8] != 2'b11)) ||
           (InstructReg[15:12] == 4'h9) ||
          ((InstructReg[15:12] == 4'h8) &&
             ((InstructReg[11] == 0) || (InstructReg[11:8]==4'h8) ||
             (InstructReg[11:10]==2'b11))) ||
             (InstructReg[15:8] == 8'h77) || (InstructReg[15:8] == 8'h72) ||
             ((InstructReg[15:12] == 4'hA) && (InstructReg[9:8] == 2'b11)
              && (InstructReg[11] || (InstructReg[11:10] == 2'b0))) ||
             (BlkMovSrcDec | (DFCDstDec & ~TBLWDec) | TBLRDec))
            EarlyWriteDec = 1;
        else
            EarlyWriteDec = 0;

        // Idle instructions
        if ((InstructReg[15:4] == 12'hBE2) & InstructReg[1])
            IdleDec = 1;
        else IdleDec = 0;

        // Delay push for interrupt call following CALL or BCR delayed instruction
        DelIntrPushDec = (ExCntrlReg[2] | ExCntrlReg[4] | ExCntrlReg[7]) & BCREnable & IntrIns;
    end
    else
    begin
        RetDec = 0;
        PLULDec = 0;
        PLUIDec = 0;
        EarlyWriteDec = 0;
        IntrDec = 0;
        TrapDec = 0;
        NMIDec = 0;
        BrnchDec = 0;
        CallDec = 0;
        BCAccDec = 0;
        DelDec = 0;
        BCRStallInsDec = 0;
        iLARd = 0;
        iLARsi = 0;
        iLARli = 0;
        LARDec = 0;
        DFCDstDec = 0;
        BlkMovSrcDec = 0;
        TBLRDec = 0;
        TBLWDec = 0;
        MadMacDec = 0;
        DPMovDec = 0;
        IODec = 0;
        MMRDec = 0;
        XCDec = 0;
        DFCSrcDec = 0;
        DFCWr = 0;
        DFCProg = 0;
        DFCReg = 0;
        IdleDec = 0;
        DelIntrPushDec = 0;
    end
end

// Repeat instruction
always @(InstructReg or OpReg or EnableDec or OpCntrlReg)
    RPTInsDec = ((!InstructReg[15:12] || (InstructReg[15:12] == 4'hB))
                 & (InstructReg[11:8] == 4'hB) & EnableDec)
                | ((OpReg[15:4] == 12'hBEC) & OpCntrlReg[0]);

// Instruction enable for interrupt insertion
always @(InsDec or InsDel or Stall or InsCycle)
    InsEnab = (InsDec & (~Stall | InsDel) & (InsCycle | Stall));

// Disable interrupts for LAR type stalls
always @(BlkMovStallDec or LdDPStallDec or LdSTStallDec or RPTStallDec or
    LARStallDec or TBLRStallDec or ExCntrlReg)
    IntrDisStall = (BlkMovStallDec | LdDPStallDec | LdSTStallDec | RPTStallDec |
                   LARStallDec | TBLRStallDec) & ExCntrlReg[5];

// Delay interrupt if XC, BCR, immediate or RPT instruction just loaded into pipeline
always @(MemCycle or InsEnab or XCDec or XC2 or BCRDec or BCRStallInsDec
       or OpCntrlReg or ExCntrlReg or IdleEx or BCREnable or RPTInsDec or RPTCZero or
       IntrDisStall)
    StuffEnab = (InsEnab | OpCntrlReg[13] | ~MemCycle) &
         ~(RPTCZero & (XCDec | XC2 | IntrDisStall |
         (BCRDec & (~OpCntrlReg[13] | OpCntrlReg[12])) | BCRStallInsDec |
         (ExCntrlReg[1] & BCREnable & ExCntrlReg[5]) | IdleEx | RPTInsDec))
         & ~(~OpCntrlReg[1] & ~MemCycle);

// Execute control decode
always @(OpReg or OpCntrlReg or ExCntrlReg or LARCntrlReg or RPTBDec or InstructReg or
         ARZ or NBIO or TC or AccNZ or AccLZ or OV or C or LdDPPrgDec or LdPMDec or BCREnable)
begin
    // Immediate instruction delayed
    ImmDelDec = ExCntrlReg[1] & BCREnable & ~ExCntrlReg[5];

    if (OpCntrlReg[0])
    begin
        // Test BCRX conditions
        TestCndDec = OpReg[15] & OpReg[14] & OpReg[13];

        // Conditional BANZ instruction
        if ((OpCntrlReg[9] & OpReg[11] & OpReg[9] & OpReg[8]) & ARZ)
            BANZEnable = 0;
        else BANZEnable = 1;

        // ProgBus source
        if (LARCntrlReg[2])
            ProgBusDec = 3'b100;
        else if (LARCntrlReg[1] | LdDPPrgDec | LdPMDec)
            ProgBusDec = 3'b010;
        else if ((OpCntrlReg[3] & OpReg[10]) || OpCntrlReg[4] || RPTBDec ||
                ((OpReg[15:8] == 8'hBE) && (OpReg[7:6] == 2'b10)) ||
                ((OpReg[15:8] == 8'hBF) && (OpReg[7] & ~(OpReg[6] & OpReg[5]))) ||
                ((OpCntrlReg[9] | OpCntrlReg[10]) & ~OpCntrlReg[11]) ||
                ((InstructReg[15:12] == 4'h7) && (InstructReg[11] & ~InstructReg[9] & ~InstructReg[8])))
            ProgBusDec = 3'b001;
        else
            ProgBusDec = 3'b000;

        // Immediate instruction
        if ((OpReg[15:11] == 5'b01111) && BANZEnable &&
           ((OpReg[9:8] == 2'b01) ||
            (OpReg[9:8] == 2'b10) ||
            (OpReg[9:8] == 2'b11)))
            ImmDec = 1;
        else if (TestCndDec & ~OpReg[10] & BANZEnable)
            ImmDec = 1;
        else
            ImmDec = 0;

        // Branch/Call/Return instruction
        BCRDec = (OpCntrlReg[2] | OpCntrlReg[6] | OpCntrlReg[7] | OpCntrlReg[8] |
                 OpCntrlReg[9] | OpCntrlReg[10]) & BANZEnable;

    end
    else
    begin
        ProgBusDec = 3'b000;
        ImmDec = 0;
        BCRDec = 0;
        BANZEnable = 1;
        TestCndDec = 0;
    end
end
 
// Program address control decode
always @(ImmDec or OpReg or OpCntrlReg or RPTCZero or BANZEnable or EnableDec
    or IntrIns or IntrOp or InsCycle or DelIntrPush)
begin
    if (OpCntrlReg[2] & OpCntrlReg[0] & BANZEnable)
        PCSelDec = 3'b010;
    else if ((OpCntrlReg[6] | OpCntrlReg[7] | OpCntrlReg[8]) & BANZEnable)
        PCSelDec = 3'b101;
    else if (OpCntrlReg[11])
        PCSelDec = 3'b011;
    else if (ImmDec)
        PCSelDec = 3'b100;
    else
        PCSelDec = 3'b001;
    if (OpCntrlReg[0])
    begin
        if (OpReg[15:0] == 16'hBE3C) iPUSHDec = 1;
        else iPUSHDec = 0;
        if (OpReg[15:8] == 8'h76) PSHDDec = 1;