m3s017ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Instruction Decode
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.114

// Revision history
// V1.114 - 27 April 1998
//        - StuffEnab disabled when LAR,LDP,LST,TBLR,BLDD instruction loaded after
//        - a delayed branch/call/return.
// V1.113 - 16 December 1996
//        - StuffEnab disabled during stall following long immediate instruction.
//        - IFnEx generated when fetched instruction will not be executed.
// V1.112 - 10 December 1996
//        - ClrOV gated with ExecuteReg[1] so OV only cleared when tested.
// V1.111 - DPMovDec exported to higher level
// V1.110 - Data reads following RETCD problem fixed

// m3s017ct
// M320C50 Instruction decode
// Performs instruction decode and loads control registers.
//
// OpCntrlReg usage:
//      0 : Decode enable (1 = enabled, 0 = disabled)
//      1 : Opcode (1 = opcode, 0 = operand)
//      2 : Return instruction
//      3 : PLU logical operation
//      4 : PLU immediate operation
//      5 : Write operation
//      6 : Interrupt instruction
//      7 : TRAP instruction
//      8 : NMI instruction
//      9 : Branch instruction
//     10 : Call instruction
//     11 : Branch/Call accumulator instruction
//     12 : Delayed instruction
//     13 : BCR stall
//     14 : LAR instruction
//     15 : Use DFC as write address
//     16 : Use DFC as read address
//     17 : Table write instruction
//     18 : I/O instruction
//     19 : MAD/MAC instruction
//     20 : Data to Prog mov instruction
//     21 : Table read instruction
//     22 : MMR instruction
//
// ExCntrlReg usage:
//      0 : Decode enable
//      1 : Immediate instruction
//      2 : Immediate instruction delayed
//      3 : Branch/call/ret instruction
//      4 : Call instruction (1 = call)
//      5 : Delayed instruction (1 = delayed)
//      6 : DFC instruction
//      7 : Ret instruction
//      8 : Interrupt/Trap/NMI instruction
//
// ProgBusDec usage:
//      0 : ProgBus = OpReg
//      1 : ProgBus = Short Immediate
//      2 : ProgBus = Long Immediate
//
// LdCntrlReg usage:
//      0 : Load DP from data bus
//      1 : Load DP from program bus
//
// PACntrlReg usage:
//    2-0 : PC select lines
//    4-3 : Stack select lines
//      5 : Push stack
//      6 : Pop stack
//      7 : Load block repeat registers
//
// DRCntrlReg usage:
//      0 : Read request
//      1 : Read indirect
//      2 : Read immediate
//      3 : Suppress Data Page
//
// DWCntrlReg usage:
//      0 : Write request
//      1 : Write indirect
//      2 : Write immediate
//      3 : Suppress Data Page
//      4 : DMOV write
//
// AuxCntrlReg usage:
//      0 : Load ST0
//      1 : Load ST1
//      2 : Read ST0
//      3 : Read ST1
//      4 : LAR from data bus
//      5 : LAR from prog bus
//
// IndCntrlReg usage:
//      0 : Modify AR
//      1 : Load ARP
//      2 : Aux Reg compare with ARCR
//      3 : Short Immediate operand
//    7:4 : ARAU control
//      8 : Store Aux Reg
//
// LARCntrlReg usage:
//      0 : LAR dma
//      1 : LAR short imm
//      2 : LAR long imm
//
// PLUCntrlReg usage:
//    1:0 : Logical operation select
//      2 : Immediate
//      3 : Logical operation enable
//      4 : SPLK operation
//
// CALURegCntrl usage:
//     0 : TReg0 load
//     1 : PReg load
//     2 : PReg high load
//     3 : Acc load
//     4 : ST0 load
//     5 : ST1 load
//     6 : PReg low store
//     7 : PReg high store
//     8 : Acc store
//     9 : AccB load
//    10 : Clear Acc
//    11 : Clear PReg
//    12 : ST0 store
//    13 : ST1 store
//    14 : Load PM bits
//
// CALUSelCntrl usage:
//      0 : Data source (0=Data, 1=Prog)
//      1 : Pre-scaler source is TReg1
//      2 : Pre-Scaler source is TReg3
//      3 : Pre-scaler shift left 16
//      4 : Pre-scaler shift left 16 with rounding (ZALR)
//      5 : Suppress sign-extension
//    9:6 : CALU shift value and AR address
//
// ALUCntrlReg usage:
//    2:0 : ALU function
//      3 : ALU source is ACCB
//      4 : ALU source is PReg
//      5 : ALU Carry input enable
//      6 : ALU NEG
//      7 : ALU ABS
//      8 : ALU SUBC
//      9 : ALU CRGT
//     10 : ALU CRLT
//     11 : ALU NORM
//
// SRCntrlReg usage:
//      0 : Enable shift/rotate
//      1 : Shift/rotate left (0=right, 1=left)
//      2 : Rotate (0=shift, 1=rotate)
//      3 : Include accumulator buffer
//      4 : BSAR instruction
//      5 : SATH instruction
//      6 : SATL instruction
//
// SetClrCntrl usage:
//      0 : Set/Clr value (1 = Set, 0 = Clear)
//      1 : OVM bit
//      2 : CNF bit
//      3 : SXM bit
//      4 : TC bit
//      5 : XF bit
//      6 : C bit
//      7 : HM bit
//      8 : INTM bit


module m3s017ct (Clock, Reset, AdvPipe, MemCycle, InsCycle, FCycDec,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
        ARZ, NBIO, TC, AccNZ, AccLZ, OV, C,
        RPTCZero, InstructReg, OpReg, ExecuteReg, IntrIns, IntrOp,
        BlkMovStall, LdDPStall, LdSTStall, LARStall, BCRStall, TBLRStall,
	Stall, CycCntrlReg, MMRins, IOins, OpCntrlReg, ExCntrlReg,
        DRCntrlRegDec, DRpCntrlRegDec, DWCntrlRegDec, LdCntrlReg,
        AuxCntrlReg, IndCntrlReg, PLUCntrlReg, ProgBusDec, MultCntrl, ClrOV, BitTestEnab,
        DFCReg, DFCProg, DFCWr, ClrcIntmDec, StAccDec, MadMacDec, BCRDec,
        BCREnable, StuffEnab, IdleDec, iIdle, iIdle2, IFnEx,
        CALURegCntrlReg, NextCALUSelCntrlReg, ALUCntrlReg, SRCntrlReg, SetClrCntrl,
        BlkMovStallDec, LdDPStallDec, LdSTStallDec, RPTStallDec, LARStallDec,
        TBLRStallDec, RPTBDec, PopDec, PushDec, StackSelDec, PCSelDec, DPMovDec);
    input        Clock, Reset, AdvPipe, MemCycle, InsCycle, FCycDec;
    input        ARZ, NBIO, TC, AccNZ, AccLZ,OV, C;
    input        CycCntrlReg, RPTCZero, IntrIns, IntrOp;
    input        MMRins, IOins, Stall;
    input        BlkMovStall, LdDPStall, LdSTStall, LARStall, BCRStall, TBLRStall;
    input [15:0] InstructReg, OpReg, ExecuteReg;
    output [22:0] OpCntrlReg;
    output [8:0] ExCntrlReg;
    output [3:0] DRCntrlRegDec, DRpCntrlRegDec;
    output [4:0] DWCntrlRegDec;
    output [1:0] LdCntrlReg;
    output [5:0] AuxCntrlReg;
    output [8:0] IndCntrlReg;
    output [4:0] PLUCntrlReg;
    output [2:0] ProgBusDec;
    output [14:0] CALURegCntrlReg;
    output [9:0] NextCALUSelCntrlReg;
    output [11:0] ALUCntrlReg;
    output [6:0] SRCntrlReg;
    output [8:0] SetClrCntrl;
    output [2:0] PCSelDec;
    output [2:0] StackSelDec;
    output       DFCReg, DFCProg, DFCWr, MultCntrl;
    output       ClrOV, BitTestEnab, IdleDec, iIdle, iIdle2;
    output       ClrcIntmDec, StuffEnab, StAccDec, MadMacDec;
    output       BlkMovStallDec, LdDPStallDec, LdSTStallDec, RPTStallDec;
    output       LARStallDec, TBLRStallDec, IFnEx;
    output       RPTBDec, PopDec, PushDec, BCRDec, BCREnable, DPMovDec;

    wire [22:0] OpCntrlReg;
    wire [8:0] ExCntrlReg;
    reg [22:0] NextOpCntrlReg;
    reg [8:0] NextExCntrlReg;
    reg [3:0] DRCntrlRegDec, DRCntrlReg, DRpCntrlRegDec, DRpCntrlReg;
    reg [4:0] DWCntrlRegDec, DWCntrlReg;
    reg [1:0] LdCntrlReg;
    wire [5:0] AuxCntrlReg;
    reg [5:0] NextAuxCntrlReg;
    wire [8:0] IndCntrlReg;
    reg [4:0] PLUCntrlReg;
    wire [14:0] CALURegCntrlReg;
    wire [9:0] CALUSelCntrlReg;
    wire [11:0] ALUCntrlReg;
    wire [6:0] SRCntrlReg;
    reg [14:0] NextCALURegCntrlReg;
    reg [9:0] NextCALUSelCntrlReg;
    reg [11:0] NextALUCntrlReg;
    reg [6:0] NextSRCntrlReg;
    reg [8:0] SetClrCntrl;
    reg [2:0] LARCntrlReg;
    reg OpcodeDec, InsDec, LoadPipe;
    reg MultCntrl;
    reg TestCndDec, TestCnd, ClrOV, BitTestEnab, BitTestEnabDec;
    reg TableIns, IODec, XCDel, XCSkip;
    reg [2:0] ProgBusDec;
    reg ImmDec, BCRDec, CallDec, DelDec, RetDec, EnableDec, ImmDelDec;
    reg LdDPDatDec, LdDPPrgDec;
    reg PushDec, PopDec, IntrDec, TrapDec, NMIDec, BrnchDec, BCAccDec;
    reg DFCReg, DFCProg, DFCWr, LARDec;
    reg [2:0] PCSelDec;
    reg [2:0] StackSelDec;
    reg WriteDec, WrIndirDec, WrImmDec, WrSupDPDec, WrDMOVDec;
    reg LdST0Dec, LdST1Dec, RdST0Dec, RdST1Dec, LARdDec, LARpDec;
    reg PLULDec, PLUIDec, EarlyWriteDec;
    reg iB, iBANZ, iBCND, iBACC, iCALL, iCALA, iCC, BCRnD, BANZEnable;
    reg iLARd, iLARsi, iLARli, SetClrDec, ClrcIntmDec;
    reg iPUSHDec, PSHDDec, iPOPDec, POPDDec;
    reg ST1Dec, ST0Dec, SPHDec, SPLDec, LPHDec, LdPDec, LdTRDec;
    reg LdAccDec, StAccDec, LdAccBDec, ClrAccDec, ClrPRegDec;
    reg PreShftLow, PreShftHigh, PreEnab, TableOp, DPMovDec;
    reg CALUSrcDec, PreTR1Dec, PreTR2Dec, PreSL16Dec, PreZALRDec, PreSuppDec;
    reg [3:0] ShiftDec;
    reg [2:0] ALUFunctionDec;
    reg ALUSrcAccBDec, ALUSrcPRegDec, ALUCEnabDec, ALUNegDec, ALUAbsDec, ALUSubCDec;
    reg ALUCrGtDec, ALUCrLtDec, ALUNormDec, BCRStallInsDec;
    reg SREnabDec, SRLeftDec, SRRotDec, SRIncBDec, SRBSARDec, SRSATHDec, SRSATLDec;
    reg DFCDstDec, BlkMovSrcDec, MadMacDec, DFCSrcDec, Macs, iMPYU, LdPMDec;
    reg RPTBDec, TBLRDec, TBLWDec, MMRDec, IdleDec, iIdle, iIdle2;
    reg BlkMovStallDec, LdDPStallDec, LdSTStallDec, RPTStallDec, LARStallDec;
    reg TBLRStallDec, BCRnDDec, BCRSkip, RPTInsDec;
    reg DelIntrPushDec, DelIntrPush, XCDec, XCi, XC2, IdleEx, StuffEnab;
    wire XCDis, BCREnable, EnableADec;
    reg ReadDec, RdIndirDec, RdImmDec, RdSupDPDec, InsDel, InsEnab;
    reg IFDis, IFDel, IFnEx, IntrDisStall;

// Crtical register muxes
always @(InsCycle or LoadPipe or LARStall or BlkMovStall or OpCntrlReg or ExCntrlReg
  or MMRDec or TBLRDec or DPMovDec or MadMacDec or IODec or TBLWDec or DFCSrcDec or DFCDstDec
  or LARDec or BCRStallInsDec or DelDec or BCAccDec or CallDec or BrnchDec
  or NMIDec or TrapDec or IntrDec or EarlyWriteDec or PLUIDec or PLULDec or RetDec
  or InsDec or EnableDec or BANZEnable or DFCProg or BCRDec or ImmDelDec or ImmDec
  or LdPMDec or ST1Dec or ST0Dec or ClrPRegDec or ClrAccDec or LdAccBDec or StAccDec
  or SPHDec or SPLDec or LdST1Dec or LdST0Dec or LdAccDec or LPHDec or LdPDec or LdTRDec
  or ALUNormDec or ALUCrLtDec or ALUCrGtDec or ALUSubCDec or ALUAbsDec or ALUNegDec
  or ALUCEnabDec or ALUSrcPRegDec or ALUSrcAccBDec or ALUFunctionDec
  or SRSATLDec or SRSATHDec or SRBSARDec or SRIncBDec or SRRotDec or SRLeftDec or SREnabDec
  or ShiftDec or PreSuppDec or PreZALRDec or PreSL16Dec or PreTR2Dec or PreTR1Dec or CALUSrcDec
  or LARpDec or LARdDec or RdST1Dec or RdST0Dec or LdST1Dec or LdST0Dec
  or OpCntrlReg or ExCntrlReg or AuxCntrlReg or CALURegCntrlReg or CALUSelCntrlReg
  or ALUCntrlReg or SRCntrlReg)
begin
    if (LoadPipe & (InsCycle | (ExCntrlReg[7] & ~ExCntrlReg[5])))
        NextOpCntrlReg = {MMRDec,TBLRDec,DPMovDec,MadMacDec,IODec,TBLWDec,DFCSrcDec,DFCDstDec,
                          LARDec,BCRStallInsDec,DelDec,BCAccDec,CallDec,BrnchDec,
                          NMIDec,TrapDec,IntrDec,EarlyWriteDec,PLUIDec,PLULDec,RetDec,
                          InsDec,EnableDec};
    else
        NextOpCntrlReg = OpCntrlReg;
    if (InsCycle & LoadPipe)
    begin
        NextExCntrlReg = {(OpCntrlReg[6] | OpCntrlReg[7] | OpCntrlReg[8]),
                          (OpCntrlReg[2] & BANZEnable),
                          DFCProg & ~OpCntrlReg[19],
                          (OpCntrlReg[12] & BANZEnable),
                          (OpCntrlReg[10] & BANZEnable),
                          BCRDec,ImmDelDec,ImmDec,OpCntrlReg[0]};
        NextCALURegCntrlReg = {LdPMDec,ST1Dec,ST0Dec,ClrPRegDec,ClrAccDec,LdAccBDec,StAccDec,
                          SPHDec,SPLDec,LdST1Dec,LdST0Dec,LdAccDec,LPHDec,LdPDec,LdTRDec};
        NextALUCntrlReg = {ALUNormDec,ALUCrLtDec,ALUCrGtDec,ALUSubCDec,ALUAbsDec,ALUNegDec,
                          ALUCEnabDec,ALUSrcPRegDec,ALUSrcAccBDec,ALUFunctionDec};
        NextSRCntrlReg = {SRSATLDec,SRSATHDec,SRBSARDec,
                          SRIncBDec,SRRotDec,SRLeftDec,SREnabDec};
    end
    else
    begin
        NextExCntrlReg = ExCntrlReg;
        NextCALURegCntrlReg = CALURegCntrlReg;
        NextALUCntrlReg = ALUCntrlReg;
        NextSRCntrlReg = SRCntrlReg;
    end
    if (LoadPipe & (InsCycle | LARStall))
        NextCALUSelCntrlReg = {ShiftDec,PreSuppDec,PreZALRDec,PreSL16Dec,
                          PreTR2Dec,PreTR1Dec,CALUSrcDec};
    else
        NextCALUSelCntrlReg = CALUSelCntrlReg;
    if (LoadPipe & (InsCycle | (LARStall & ~BlkMovStall)))
        NextAuxCntrlReg[5:4] = {LARpDec,LARdDec};
    else
        NextAuxCntrlReg[5:4] = AuxCntrlReg[5:4];
    if (LoadPipe & InsCycle)
        NextAuxCntrlReg[3:0] = {RdST1Dec,RdST0Dec,LdST1Dec,LdST0Dec};
    else
        NextAuxCntrlReg[3:0] = AuxCntrlReg[3:0];
end

// Critical registers
m3s051ct U1 (Clock, Reset, MemCycle,
  NextOpCntrlReg, NextExCntrlReg, NextCALURegCntrlReg, NextALUCntrlReg,
  NextSRCntrlReg, NextCALUSelCntrlReg, NextAuxCntrlReg,
  OpCntrlReg, ExCntrlReg, CALURegCntrlReg, ALUCntrlReg, SRCntrlReg,
  CALUSelCntrlReg, AuxCntrlReg);

// Control registers
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        DRCntrlReg <= 0;
        DRpCntrlReg <= 0;
        DWCntrlReg <= 0;
        LdCntrlReg <= 0;
        PLUCntrlReg <= 0;
        LARCntrlReg <= 0;
        MultCntrl <= 0;
        LoadPipe <= 0;
        TableIns <= 0;
        TableOp <= 0;
        TestCnd <= 0;
        BitTestEnab <= 0;
        BCRnD <= 0;
        XCDel <= 0;
        XCi <= 0;
        XC2 <= 0;
        iIdle <= 0;
        iIdle2 <= 0;
        DelIntrPush <= 0;
        IdleEx <= 0;
        InsDel <= 0;
        IFDel <= 0;
    end
    else
    begin
        LoadPipe <= 1;
        if (MemCycle)
        begin
            DRCntrlReg <= DRCntrlRegDec;
            DRpCntrlReg <= DRpCntrlRegDec;
            DWCntrlReg <= DWCntrlRegDec;
            DelIntrPush <= DelIntrPushDec & InsCycle;
            InsDel <= InsDec;
            IFDel <= IFDis;
        end
        if (AdvPipe | BCRStall)
            begin