m3s072ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// ALU and Accumulator
// Copyright Mentor Graphics Corporation and licensors 1998.
// V1.011

// Revision history
// V1.011 - 3 October 1996
//          Carry flag forced to zero for ABS instruction.
// V1.010 - 5 August 1996

// m3s072ct
// M320C50 Arithmetic-Logic Unit for CALU.
//
// RegCntrl:
//    0 : TReg0 load
//    1 : PReg load
//    2 : PReg high load
//    3 : Acc load
//    4 : ST0 load
//    5 : ST1 load
//    6 : PReg low store
//    7 : PReg high store
//    8 : Acc store
//    9 : AccB load
//   10 : Clear Acc
//   11 : Clear PReg
//
// ALUCntrl:
//  2:0 : ALU function control
//    3 : ALU source is ACCB
//    4 : ALU source is PReg
//    5 : ALU Carry input enable
//    6 : ALU NEG
//    7 : ALU ABS
//    8 : ALU SUBC
//    9 : ALU CRGT
//   10 : ALU CRLT
//   11 : ALU NORM
//
// SRCntrl:
//    0 : Enable shift/rotate
//    1 : Shift/rotate left (0=right, 1=left)
//    2 : Rotate (0=shift, 1=rotate)
//    3 : Include accumulator buffer
//    4 : BSAR instruction
//    5 : SATH instruction
//    6 : SATL instruction
//
// SelCntrl usage:
//    0 : Shift left 16
//    1 : Shift left 16 with rounding (ZALR)
//    2 : Suppress sign extension
//
// PM is the P register output scaler control
// SXM and OVM are control flags in the status register controlling
//     sign extension and overflow mode
// ClrOV clears the OV flag
// C is the ALU carry
// AccLZ and AccNZ are outputs for test values of the accumulator

module m3s072ct (DataBus, IpBus, MultOp, RegCntrl, ALUCntrl, SRCntrl,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  PM, ClrOV, SXM, OVM, LoadC, LoadCValue, LastMemCycle,
  PreScalerShift, BarrelShift, PostScalerShift, SelCntrl,
  ContextSave, ContextRestore, DMAMode, Clock, MemCycle, Reset,
  C, OV, AccNZ, AccLZ, NormEnab, BitTest, DataWrite);

  input [15:0] DataBus, IpBus;
  input [31:0] MultOp;
  input [11:0] RegCntrl;
  input [11:0] ALUCntrl;
  input [6:0] SRCntrl;
  input [2:0] SelCntrl;
  input ContextSave, ContextRestore, DMAMode;
  input [1:0] PM;
  input Clock, MemCycle, Reset, LastMemCycle;
  input SXM, OVM;
  input LoadC, LoadCValue;
  input ClrOV;
  input [4:0] BarrelShift;
  input [3:0] PreScalerShift, PostScalerShift;
  
  output [15:0] DataWrite;
  output C, OV;
  output AccNZ, AccLZ;
  output NormEnab, BitTest;

  tri  [15:0] DataWrite;
  wire [31:0] ALU_Op, PreScalerOp;
  wire        ALU_OV, CarryOut, LdCOV;
  wire [31:0] RightShiftOp, ShiftRotateOp;
  wire        BitTest;
  wire [31:0] NextPReg;
  wire  [2:0] RSSrc;
  reg [31:0] NewPReg, PReg, PReg_C;
  reg [31:0] PRegScaled;
  reg [31:0] ACC, ACC_C, ACCB, ACCB_C, NextAcc;
  reg [15:0] PRegOp;
  reg        C, C_C, NextC, CarryIn;
  reg        OV, OV_C, NextOV;
  reg        NormEnab, OVCond, OVSign;
  reg  [1:0] ShiftRotateCntrl;
  reg        TopBit, BotBit;   //top and bottom shift in bits for shift/rotate operations
  reg        AccNZ, AccLZ;
  reg        CmprACCs, AccLoad, LdMult;
  
  reg [31:0] ALU_Ip;
  
// PReg load control
always @(LastMemCycle or RegCntrl)
    LdMult = LastMemCycle & RegCntrl[1];

// PReg non-multiplier mux
always @(LastMemCycle or RegCntrl or ContextRestore or DataBus or PReg or PReg_C)
    if (LastMemCycle & RegCntrl[2])
        NewPReg <= {DataBus[15:0],PReg[15:0]};
    else if (LastMemCycle & RegCntrl[11])
        NewPReg <= 32'b0;
    else if (ContextRestore)
        NewPReg <= PReg_C;
    else
        NewPReg <= PReg;

// PReg multiplexer
m3s048ct U6 (LdMult, MultOp, NewPReg, NextPReg);

// P register
always @(posedge Clock)
begin
    PReg <= NextPReg;
    if (ContextSave)
        PReg_C <= PReg;
end

// P register scaler
always @(PReg or PM)
case (PM)
    0: PRegScaled = PReg; // no shift
    1: PRegScaled = {PReg[30:0],1'b0};
    2: PRegScaled = {PReg[27:0],4'b0};
    3: PRegScaled = {PReg[31],PReg[31],PReg[31],PReg[31],PReg[31],PReg[31],PReg[31:6]};
endcase

// P register output mux
always @(RegCntrl or PRegScaled)
    if (RegCntrl[7]) PRegOp = PRegScaled[31:16];
    else PRegOp = PRegScaled[15:0];

// ACCB register
always @(posedge Clock)
    if (LastMemCycle)
    begin
        if (SRCntrl[3])
        begin
            if (SRCntrl[1])
            begin
                ACCB[31:1] <= ACCB[30:0];
                if (SRCntrl[2])
	            ACCB[0] <= C;
                else
	            ACCB[0] <= 0;
            end
            else
            begin
                ACCB[30:0] <= ACCB[31:1];
                ACCB[31] <= ACC[0];
            end
        end
        else if (RegCntrl[9] & ~(~CmprACCs & (ALUCntrl[9] | ALUCntrl[10])))
            ACCB <= ACC;
        else if (ContextRestore)
            ACCB <= ACCB_C;
    end
always @(posedge Clock)
    if (ContextSave)
        ACCB_C <= ACCB;

// Pre-Scaler for ALU
m3s078ct U2 (PreScalerOp, IpBus, PreScalerShift, SelCntrl, SXM);

assign BitTest = PreScalerOp[15];

// ALU input mux
always @(ALUCntrl or PreScalerOp or PRegScaled or ACCB)
case (ALUCntrl[4:3])
    0: ALU_Ip = PreScalerOp;
    1: ALU_Ip = ACCB;
    2: ALU_Ip = PRegScaled;
    3: ALU_Ip = ACCB;
endcase

// ALU itself!
m3s073ct U1 (ALU_Op, ACC, ALU_Ip, CarryIn, CarryOut,
    ALU_OV, ALUCntrl[2:0], ALUCntrl[7], ALUCntrl[6], LdCOV);

// select ACC source for conditional feedback instructions
m3s053ct U5 (ALUCntrl[10:7], {SRCntrl[6:4],SRCntrl[0]},
  ACC[31], CarryOut, ALU_Op[31], ALU_OV, RSSrc);

// generate overflow control flag
always @(ALUCntrl or LdCOV or OVM or ALU_OV)
    OVCond = ~ALUCntrl[8] & LdCOV & OVM & ALU_OV;

// generate normalisation control bit
always @(ACC or ALUCntrl or AccNZ)
    NormEnab = (ACC[31] ~^ ACC[30]) & ALUCntrl[11] & AccNZ;

// genrate ShiftRotateCntrl, control for shift/rotate
always @(SRCntrl or ALUCntrl or OVCond or NormEnab)
    if ((SRCntrl[0] & SRCntrl[1]) | NormEnab | ALUCntrl[8])
        ShiftRotateCntrl = 2;
    else if (SRCntrl[0] & ~ALUCntrl[11])
        ShiftRotateCntrl = 1;
    else if (OVCond)
        ShiftRotateCntrl = 3;
    else
        ShiftRotateCntrl = 0;

// Overflow sign
always @(ALUCntrl or ACC)
    OVSign = (ALUCntrl[6] | ALUCntrl[7]) ^ ACC[31];

// generate bottom bit for shift/rotate
always @(SRCntrl or ALUCntrl or ACCB or C or OVSign or CarryOut)
case ({ALUCntrl[8],SRCntrl[3:2],SRCntrl[0]})
    0: BotBit = ~OVSign;
    1: BotBit = 0;
    2: BotBit = C;
    3: BotBit = C;
    4: BotBit = ACCB[31];
    5: BotBit = ACCB[31];
    6: BotBit = ACCB[31];
    7: BotBit = ACCB[31];
    default: BotBit = CarryOut;
endcase

// generate top bit for shift/rotate
always @(SRCntrl or C or OVSign or ACC or SXM)
case ({SRCntrl[2],SRCntrl[0]})
    0: TopBit = OVSign;
    1: TopBit = SXM & ACC[31];
    2: TopBit = C;
    3: TopBit = C;
endcase

// Accumulator right only barrel shift
m3s079ct U3 (RightShiftOp, ACC, BarrelShift, SRCntrl[6:4], SXM);

// ALU output scaler and accumulator shift/rotate mux
m3s077ct U4 (ALU_Op, RightShiftOp, ACCB, ShiftRotateOp, ShiftRotateCntrl, RSSrc, TopBit, BotBit);

// *****ACCUMULATOR*****
always @(Reset or LastMemCycle or RegCntrl or ContextRestore
        or ShiftRotateOp or ACC_C or ACC)
begin
    if (RegCntrl[10] | Reset)
        NextAcc = 32'b0;
    else if (LastMemCycle & RegCntrl[3])
        NextAcc = ShiftRotateOp;
    else if (ContextRestore)
        NextAcc = ACC_C;
    else
        NextAcc = ACC;
    AccLoad = LastMemCycle | Reset;
end

always @(posedge Clock)
    if (AccLoad)
        ACC <= NextAcc;

always @(posedge Clock)
    if (ContextSave)
        ACC_C <= ACC;

// Accumulator value tests
always @(posedge Clock)
    if (MemCycle)
    begin
        AccNZ <= (NextAcc != 32'b0);
        AccLZ <= NextAcc[31];
    end

// Result of comparison of ACC and ACCB
// For CRGT instruction CmprACCs=1 if ACC >= ACCB
// For CRLT instruction CmprACCs=1 if ACC < ACCB
always @(ALUCntrl or ALU_OV or ALU_Op)
    CmprACCs = ((ALU_OV ~^ ALU_Op[31]) & ALUCntrl[9])
             | (~(ALU_OV ~^ ALU_Op[31]) & ALUCntrl[10]);

// Carry bit
always @(Reset or SRCntrl or LdCOV or RegCntrl or LoadC or ALUCntrl
  or ContextRestore or ACC or ACCB or CarryOut or LoadCValue or CmprACCs
  or DataBus or C_C or C or LastMemCycle or SelCntrl)
    if (LastMemCycle & ((SRCntrl[1] & ~ ALUCntrl[11])
        | SRCntrl[3] | (SRCntrl[0] & ~ALUCntrl[11])
        | ALUCntrl[9] | ALUCntrl[10] | ALUCntrl[8]
        | LdCOV | RegCntrl[5] | LoadC | ContextRestore))
        NextC = (SRCntrl[1] & ~ALUCntrl[11] & ACC[31])
            | (SRCntrl[3] & ~(SRCntrl[1] & ~ALUCntrl[11]) & ACCB[0])
            | (SRCntrl[0] & ~ALUCntrl[11] & ~(SRCntrl[1] | SRCntrl[3]) & ACC[0])
            | ((ALUCntrl[9] | ALUCntrl[10]) & CmprACCs)
            | (LdCOV & ~(ALUCntrl[7] | ALUCntrl[8] | ALUCntrl[9] | ALUCntrl[10] | SelCntrl[0]) & CarryOut)
            | (LdCOV & SelCntrl[0] & ~ALUCntrl[1] & (CarryOut | C))
            | (LdCOV & SelCntrl[0] & ALUCntrl[1] & (CarryOut & C))
            | (RegCntrl[5] & DataBus[9])
            | (LoadC & LoadCValue)
            | (ContextRestore & C_C);
    else
        NextC = C | Reset;

always @(posedge Clock)
    C <= NextC;

// derive carry input into ALU
always @(ALUCntrl or C)
    CarryIn = ALUCntrl[6] | ALUCntrl[7] | (ALUCntrl[5] & C)
        | ((ALUCntrl[2:0] == 3'o6) & ~ALUCntrl[5]);

// context save value for carry
always @(posedge Clock)
    if (ContextSave)
        C_C <= NextC;

// Overflow bit
always @(Reset or LdCOV or RegCntrl or ClrOV or ContextRestore
  or ALU_OV or DataBus or OV_C or OV or MemCycle or LastMemCycle)
    if (LdCOV & ~OV & LastMemCycle)
        NextOV = ALU_OV;
    else if (RegCntrl[4] & LastMemCycle)
        NextOV = DataBus[12];
    else if ((ClrOV & MemCycle) | Reset)
        NextOV = 0;
    else if (ContextRestore & LastMemCycle)
        NextOV = OV_C;
    else
        NextOV = OV;
always @(posedge Clock)
    OV <= NextOV;

// context save value for OV
always @(posedge Clock)
    if (ContextSave)
        OV_C <= NextOV;

// Post-Scaler
m3s088ct U7 (ACC, PostScalerShift, RegCntrl[8], DMAMode, DataWrite);


assign DataWrite = ((RegCntrl[7] | RegCntrl[6]) & ~DMAMode) ? PRegOp : 16'bZ;

endmodule