📄 m3s051ct.v
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//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra //// Instruction Decoder Latches// Copyright Mentor Graphics Corporation and Licensors 1998.// V1.000// m3s051ct// M320C50 Latches for use in Instruction Decoder block.// These latches, together with the MemCycle control line are in a// separate block to prevent the synthesiser from mixing MemCycle with// the decoding logic.`define C_ExCntrlRst 9'h040module m3s051ct (Clock, Reset, MemCycle,//******************************************************************* ////IMPORTANT NOTICE ////================ ////Copyright Mentor Graphics Corporation 1996 - 1998. All rights reserved. ////This file and associated deliverables are the trade secrets, ////confidential information and copyrighted works of Mentor Graphics ////Corporation and its licensors and are subject to your license agreement ////with Mentor Graphics Corporation. //// ////These deliverables may be used for the purpose of making silicon for one ////IC design only. No further use of these deliverables for the purpose of ////making silicon from an IC design is permitted without the payment of an ////additional license fee. See your license agreement with Mentor Graphics ////for further details. If you have further questions please contact ////Mentor Graphics Customer Support. //// ////This Mentor Graphics core (m320c50eng v1999.010) was extracted on ////workstation hostid 800059c1 Inventra // NextOpCntrlReg, NextExCntrlReg, NextCALURegCntrlReg, NextALUCntrlReg, NextSRCntrlReg, NextCALUSelCntrlReg, NextAuxCntrlReg, OpCntrlReg, ExCntrlReg, CALURegCntrlReg, ALUCntrlReg, SRCntrlReg, CALUSelCntrlReg, AuxCntrlReg); input Clock, Reset, MemCycle; input [22:0] NextOpCntrlReg; input [8:0] NextExCntrlReg; input [14:0] NextCALURegCntrlReg; input [11:0] NextALUCntrlReg; input [6:0] NextSRCntrlReg; input [9:0] NextCALUSelCntrlReg; input [5:0] NextAuxCntrlReg; output [22:0] OpCntrlReg; output [8:0] ExCntrlReg; output [14:0] CALURegCntrlReg; output [11:0] ALUCntrlReg; output [6:0] SRCntrlReg; output [9:0] CALUSelCntrlReg; output [5:0] AuxCntrlReg; reg [22:0] OpCntrlReg; reg [8:0] ExCntrlReg; reg [14:0] CALURegCntrlReg; reg [11:0] ALUCntrlReg; reg [6:0] SRCntrlReg; reg [9:0] CALUSelCntrlReg; reg [5:0] AuxCntrlReg;always @(posedge Clock or posedge Reset) if (Reset) begin OpCntrlReg <= 0; ExCntrlReg <= `C_ExCntrlRst; CALURegCntrlReg <= 0; ALUCntrlReg <= 0; SRCntrlReg <= 0; CALUSelCntrlReg <= 0; AuxCntrlReg <= 0; end else if (MemCycle) begin OpCntrlReg <= NextOpCntrlReg; ExCntrlReg <= NextExCntrlReg; CALURegCntrlReg <= NextCALURegCntrlReg; ALUCntrlReg <= NextALUCntrlReg; SRCntrlReg <= NextSRCntrlReg; CALUSelCntrlReg <= NextCALUSelCntrlReg; AuxCntrlReg <= NextAuxCntrlReg; endendmodule⌨️ 快捷键说明
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