m3s057ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Program Address Generator Latches
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.000

// m3s057ct
// M320C50 Latches for use with program address generator.
// These latches, together with the MemCycle control line are in a
// separate block to prevent the synthesiser from mixing MemCycle with
// the decoding logic.

module m3s057ct (Clock, MemCycle, Reset, NextPFC, NextDFC, NextBMAR, NextProgAddr,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  NextPrDpReq, NextPrSpReq, NextPrPrReq, NextPrExReq,
  NextPwDpReq, NextPwSpReq, NextPwPrReq, NextPwExReq,
  PFC, DFC, BMAR, ProgAddr,
  PrDpReq, PrSpReq, PrPrReq, PrExReq, PwDpReq, PwSpReq, PwPrReq, PwExReq);

    input         Clock, MemCycle, Reset;
    input  [15:0] NextPFC, NextDFC, NextBMAR, NextProgAddr;
    input         NextPrDpReq, NextPrSpReq, NextPrPrReq, NextPrExReq;
    input         NextPwDpReq, NextPwSpReq, NextPwPrReq, NextPwExReq;
    output [15:0] PFC, DFC, BMAR, ProgAddr;
    output        PrDpReq, PrSpReq, PrPrReq, PrExReq;
    output        PwDpReq, PwSpReq, PwPrReq, PwExReq;

    reg [15:0] PFC, DFC, BMAR, ProgAddr;
    reg        PrDpReq, PrSpReq, PrPrReq, PrExReq;
    reg        PwDpReq, PwSpReq, PwPrReq, PwExReq;


always @(posedge Clock or posedge Reset)
if (Reset)
begin
    PFC <= 0;
    DFC <= 0;
    PrDpReq <= 0;
    PrSpReq <= 0;
    PrPrReq <= 0;
    PrExReq <= 0;
    PwDpReq <= 0;
    PwSpReq <= 0;
    PwPrReq <= 0;
    PwExReq <= 0;
end
else if (MemCycle)
begin
    PFC <= NextPFC;
    DFC <= NextDFC;
    PrDpReq <= NextPrDpReq;
    PrSpReq <= NextPrSpReq;
    PrPrReq <= NextPrPrReq;
    PrExReq <= NextPrExReq;
    PwDpReq <= NextPwDpReq;
    PwSpReq <= NextPwSpReq;
    PwPrReq <= NextPwPrReq;
    PwExReq <= NextPwExReq;
end

always @(posedge Clock)
if (MemCycle)
begin
    BMAR <= NextBMAR;
    ProgAddr <= NextProgAddr;
end

endmodule