m3s004ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Program Stack
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.102

// Revision history
// V1.102 - 20 November 1996
//          Stack output tri-states replaced by mux.

// M320C50 8-Level Clocked Program Stack
// The 16-bit input data is pushed onto the stack when Push is high,
// and popped from the stack when Pop is high.
// If stack overflow occurs the bottom of the stack is lost. If stack
// underflow occurs the last value is returned.
//
// The stack comprisses eight 16-bit registers and two 3-bit pointers
// (a top of stack pointer and a bottom of stack pointer).
//
// When Push is high the register addressed by the top of stack pointer is
// written and the top of stack pointer is incremented. If the top of stack
// pointer is the same as the bottom of stack pointer then the bottom of
// stack pointer is also incremented.
//
// When Pop is high and the top of stack pointer is not the same as the value
// above the bottom of stack pointer, the top of stack pointer is decremented,

// m3s004ct
// M320C50 Program Stack

module m3s004ct (IpBus, Push, Pop, Clock, MemCycle, Reset, OpBus);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //

    input  [15:0] IpBus;
    input         Clock, MemCycle, Reset, Push, Pop;
    output [15:0] OpBus;

    reg [15:0] OpBus;
    reg  [2:0] NextTOS, NextBOS;
    reg  [2:0] ReadPointer, NewTOS;
    reg [15:0] NextStackReg0, NextStackReg1, NextStackReg2, NextStackReg3;
    reg [15:0] NextStackReg4, NextStackReg5, NextStackReg6, NextStackReg7;
    reg [15:0] StackReg0, StackReg1, StackReg2, StackReg3;
    reg [15:0] StackReg4, StackReg5, StackReg6, StackReg7;
    reg        LastMemCycle;

    wire [2:0] TopOfStack, BotOfStack;


// Stack pointers
always @(Push or Pop or ReadPointer or TopOfStack or BotOfStack or NewTOS)
begin
if (Push) NextTOS = NewTOS;
else if (Pop & (ReadPointer != BotOfStack)) NextTOS = ReadPointer;
else NextTOS = TopOfStack;

if (Push & (BotOfStack == TopOfStack)) NextBOS = NewTOS;
else NextBOS = BotOfStack;
end

// Stack register load
always @(Push or TopOfStack or IpBus or StackReg0 or StackReg1 or StackReg2
  or StackReg3 or StackReg4 or StackReg5 or StackReg6 or StackReg7)
begin
    if (Push & (TopOfStack == 0)) NextStackReg0 = IpBus;
    else NextStackReg0 = StackReg0;
    if (Push & (TopOfStack == 1)) NextStackReg1 = IpBus;
    else NextStackReg1 = StackReg1;
    if (Push & (TopOfStack == 2)) NextStackReg2 = IpBus;
    else NextStackReg2 = StackReg2;
    if (Push & (TopOfStack == 3)) NextStackReg3 = IpBus;
    else NextStackReg3 = StackReg3;
    if (Push & (TopOfStack == 4)) NextStackReg4 = IpBus;
    else NextStackReg4 = StackReg4;
    if (Push & (TopOfStack == 5)) NextStackReg5 = IpBus;
    else NextStackReg5 = StackReg5;
    if (Push & (TopOfStack == 6)) NextStackReg6 = IpBus;
    else NextStackReg6 = StackReg6;
    if (Push & (TopOfStack == 7)) NextStackReg7 = IpBus;
    else NextStackReg7 = StackReg7;
end

// Stack pointer increment/decrement
always @(TopOfStack)
begin
    ReadPointer = TopOfStack - 1;
    NewTOS = TopOfStack + 1;
end

// Generate stack push enable
always @(posedge Clock or posedge Reset)
    if (Reset)
        LastMemCycle <= 0;
    else
        LastMemCycle <= MemCycle;

// Stack pointer registers
m3s059ct U1 (Clock, MemCycle, Reset, NextTOS, NextBOS,
  TopOfStack, BotOfStack);

// Stack Registers
always @(posedge Clock)
    if (LastMemCycle)
    begin
        StackReg0 <= NextStackReg0;
        StackReg1 <= NextStackReg1;
        StackReg2 <= NextStackReg2;
        StackReg3 <= NextStackReg3;
        StackReg4 <= NextStackReg4;
        StackReg5 <= NextStackReg5;
        StackReg6 <= NextStackReg6;
        StackReg7 <= NextStackReg7;
    end


// Output mux
always @(ReadPointer or
    StackReg0 or StackReg1 or StackReg2 or StackReg3 or
    StackReg4 or StackReg5 or StackReg6 or StackReg7)
    case (ReadPointer)
        0: OpBus = StackReg0;
        1: OpBus = StackReg1;
        2: OpBus = StackReg2;
        3: OpBus = StackReg3;
        4: OpBus = StackReg4;
        5: OpBus = StackReg5;
        6: OpBus = StackReg6;
        7: OpBus = StackReg7;
    endcase

endmodule