m3s008ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Block Repeat Controller
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.203

// Revision history
// V1.203 - 27 June 1997
//          Number of tri-state drivers reduced.
// V1.202 - 16 December 1996
//          BRCR decrement delayed and gated with IFnEx.
// V1.201 - 29 July 1996
//          Reads of BRCR pipelined by one stage for compatability.
// V1.2   - 3 June 1996
//          SetBRAF signal generated when LdPARegs and BRCR not being loaded
//          with 0.
// V1.103 - 10 May 1996

// m3s008ct
// M320C50 Block repeat controller
// Provides the three registers (PASR, PAER, and BRCR) that control the
// block repeat operation.
//
// BrptRegCntrl:
//    0    Load BRCR
//    1    Load PASR
//    2    Load PAER
//    3    Store BRCR
//    4    Store PASR
//    5    Store PAER
//


module m3s008ct (ProgBus, DataBus, PFC, PFCDec,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    Clock, MemCycle, InsCycle, LdPARegs, BrptRegCntrl, iMMR, BRAF, IFnEx,
    PASR, SelPASR, SetBRAF, ClrBRAF, DataWrite, DataRead);

    input  [15:0] ProgBus, DataBus, PFC, PFCDec;
    input         Clock, MemCycle, InsCycle;
    input   [5:0] BrptRegCntrl;
    input         LdPARegs, iMMR, BRAF, IFnEx;
    input  [15:0] DataWrite;
    output [15:0] PASR, DataRead;
    output        SelPASR, SetBRAF, ClrBRAF;

    reg  [15:0] NextPASR, NextPAER, NextBRCR, NextRdBRCR;
    reg         SelPASR, SetBRAF, ClrBRAF, Cmpr, NextBRCRZero, DelCmpr, DecBRCR;
    reg  [15:0] DataReadOp;
    wire [15:0] PASR, PAER, BRCR, RdBRCR;

// Register updates
always @(InsCycle or LdPARegs or BrptRegCntrl or iMMR or DecBRCR or PFCDec
      or ProgBus or DataBus or DataWrite or PASR or PAER or BRCR or RdBRCR)
begin
    if (InsCycle & LdPARegs) NextPASR = PFCDec;
    else if (BrptRegCntrl[1] & iMMR) NextPASR = DataBus;
    else if (BrptRegCntrl[1] & ~iMMR) NextPASR = DataWrite;
    else NextPASR = PASR;
    if (InsCycle & LdPARegs) NextPAER = ProgBus;
    else if (BrptRegCntrl[2] & iMMR) NextPAER = DataBus;
    else if (BrptRegCntrl[2] & ~iMMR) NextPAER = DataWrite;
    else NextPAER = PAER;
    if (BrptRegCntrl[0] & iMMR) NextBRCR = DataBus;
    else if (BrptRegCntrl[0] & ~iMMR) NextBRCR = DataWrite;
    else if (InsCycle & DecBRCR) NextBRCR = BRCR - 1;
    else NextBRCR = BRCR;
    if (BrptRegCntrl[0] & iMMR) NextRdBRCR = DataBus;
    else if (BrptRegCntrl[0] & ~iMMR) NextRdBRCR = DataWrite;
    else if (InsCycle) NextRdBRCR = BRCR;
    else NextRdBRCR = RdBRCR;
end

m3s058ct U1 (Clock, MemCycle, NextPASR, NextPAER, NextBRCR, NextRdBRCR,
  PASR, PAER, BRCR, RdBRCR);

// End address compare
always @(PAER or PFC)
    if (PAER == PFC) Cmpr = 1;
    else Cmpr = 0;

// Repeat counter zero detect
always @(NextBRCR)
    if (!NextBRCR) NextBRCRZero = 1;
    else NextBRCRZero = 0;

// Control signals
always @(LdPARegs or Cmpr or NextBRCRZero or BRAF or DecBRCR)
begin
    SetBRAF = LdPARegs & ~NextBRCRZero;
    SelPASR = BRAF & Cmpr;
    ClrBRAF = DecBRCR & NextBRCRZero;
end

// Delay decrement of BRCR
always @(posedge Clock)
if (InsCycle & MemCycle)
    DelCmpr <= SelPASR;
always @(DelCmpr or IFnEx)
    DecBRCR = DelCmpr & ~IFnEx;

// DataRead output mux
always @(BrptRegCntrl or RdBRCR or PASR or PAER)
    if (BrptRegCntrl[3]) DataReadOp = RdBRCR;
    else if (BrptRegCntrl[4]) DataReadOp = PASR;
    else if (BrptRegCntrl[5]) DataReadOp = PAER;
    else DataReadOp = 0;

// Output drivers
assign DataRead = (BrptRegCntrl[3] | BrptRegCntrl[4] | BrptRegCntrl[5])
     ? DataReadOp : 16'bZ;

endmodule