m3s050ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Instruction Pipeline Latches
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.003

// Revision history
// V1.003 - 20 November 1996
//          DataLatch added.

// m3s050ct
// M320C50 Latches for use in Instruction Pipeline block.
// These latches, together with the MemCycle control line are in a
// separate block to prevent the synthesiser from mixing MemCycle with
// the decoding logic.

module m3s050ct (Clock, Reset, MemCycle, IntrStuffi, ProgValid,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
  LdInsRegIp, LdInsRegLtch, PipelineIp, InstructLatch,
  NextOpReg, NextExecuteReg, NextIndpCntrlReg, NextIndsCntrlReg, NextProgImmHi,
  NextDataLatch,
  InstructReg, OpReg, ExecuteReg, IndpCntrlReg, IndsCntrlReg, ProgImmHi,
  PBInsReg, PBOpReg, DataLatch);

    input         Clock, Reset, MemCycle;
    input         IntrStuffi, ProgValid, LdInsRegIp, LdInsRegLtch;
    input  [15:0] PipelineIp, InstructLatch, NextOpReg, NextExecuteReg;
    input   [8:0] NextIndpCntrlReg, NextIndsCntrlReg;
    input   [7:0] NextProgImmHi;
    input  [15:0] NextDataLatch;
    output [15:0] InstructReg, OpReg, ExecuteReg, PBInsReg, PBOpReg;
    output  [8:0] IndpCntrlReg, IndsCntrlReg;
    output  [7:0] ProgImmHi;
    output [15:0] DataLatch;

    reg [15:0] InstructReg, OpReg, ExecuteReg, PBInsReg, PBOpReg;
    reg  [8:0] IndpCntrlReg, IndsCntrlReg;
    reg  [7:0] ProgImmHi;
    reg [15:0] NextInstructReg, DataLatch;

// NextInstructReg
always @(MemCycle or ProgValid or LdInsRegIp or IntrStuffi or LdInsRegLtch
    or PipelineIp or InstructLatch or InstructReg)
    if (IntrStuffi | (MemCycle & ProgValid & LdInsRegIp))
        NextInstructReg = PipelineIp;
    else if (MemCycle & LdInsRegLtch)
        NextInstructReg = InstructLatch;
    else 
        NextInstructReg = InstructReg;

// InstructReg
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        InstructReg <= 0;
        PBInsReg <= 0;
    end
    else
    begin
        InstructReg <= NextInstructReg;
        PBInsReg <= NextInstructReg;
    end

// Hi-byte of immediate ProgBus value and ProgBus OpReg
always @(posedge Clock)
    if (MemCycle)
    begin
        ProgImmHi <= NextProgImmHi;
        PBOpReg <= NextOpReg;
        DataLatch <= NextDataLatch;
    end

// Other registers
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        OpReg <= 0;
        ExecuteReg <= 0;
	IndpCntrlReg <= 0;
	IndsCntrlReg <= 0;
    end
    else if (MemCycle)
    begin
        OpReg <= NextOpReg;
        ExecuteReg <= NextExecuteReg;
	IndpCntrlReg <= NextIndpCntrlReg;
	IndsCntrlReg <= NextIndsCntrlReg;
    end

endmodule