m3s002ct.v

这是16位定点dsp源代码。已仿真和综合过了

                       || (((InstructReg[15:12]==4'hA) && ~InstructReg[11]) & NextRPTCZero & InsCycle)
                       || ((OpCntrlReg[17] | OpCntrlReg[21]) & InsCycle)
                       || (PADFCCntrlDec[1] & (DPMovDec | OpCntrlReg[20] | MadMacDec | OpCntrlReg[19])));

end
always @(NextPACntrl_7 or BCRDec
    or DWCntrlRegDec or AdvPipe or RPTBDec)
begin
    PAOpCntrlDec[0] = NextPACntrl_7 & ~(BCRDec & AdvPipe) & ~DWCntrlRegDec[0];
    PAOpCntrlDec[1] = NextPACntrl_7 & ~(BCRDec & AdvPipe) & DWCntrlRegDec[0];
    PAOpCntrlDec[2] = RPTBDec & AdvPipe;
end

// PACntrl[15:13] latched in Program Address Generator to allow early request decodes
always @(MadMacInsDec or BlkMovInsDec or BlkMovStallDec or SourceRPTCZero or iTBLWDec
    or DFConPADec or BlkMovPADec or BlkMovPBDec or LARStallDec or NextPrgWrEnab or InsCycle)
begin
    PACntrl[15] = BlkMovPBDec & ~(LARStallDec & InsCycle);
    PACntrl[14] = (MadMacInsDec & (BlkMovStallDec | ~SourceRPTCZero))
        | ((BlkMovInsDec & (BlkMovStallDec | ~SourceRPTCZero)) & (DFConPADec | BlkMovPADec))
        | NextPrgWrEnab | iTBLWDec;
    PACntrl[13] = iTBLWDec | NextPrgWrEnab;
end

always @(posedge Clock or posedge Reset)
if (Reset)
    PACntrlReg[7:0] <= 0;
else if (AdvPipe | BCRStall)
begin
    PACntrlReg[7:6] <= {PopDec & (AdvPipe | (ExCntrlReg[7] & BCREnable)), PushDec};
    PACntrlReg[5:0] <= {StackSelDec, PCSelDec};
end
always @(posedge Clock or posedge Reset)
if (Reset)
begin
    PAStall <= 0;
    PADFCCntrl <= 4'b0;
    PAOpCntrl <= 3'b0;
end
else if (MemCycle)
begin
    PAStall <= NextPAStall;
    PADFCCntrl <= PADFCCntrlDec;
    PAOpCntrl <= PAOpCntrlDec;
end

always @(PACntrlReg or InsCycle or OpCntrlReg or PrgWrEnab or iTBLW
    or BCRStall or NextPAStall or PADFCCntrl or PAOpCntrl or BCREnable)
begin
    if ((InsCycle & ~(OpCntrlReg[13] | PrgWrEnab | iTBLW)) | BCRStall)
    begin
        PACntrl[2] = PACntrlReg[2] & BCREnable;
        PACntrl[1] = PACntrlReg[1] & BCREnable;
        PACntrl[0] = PACntrlReg[0] | ~BCREnable;
    end
    else
        PACntrl[2:0] = 3'b0;
    PACntrl[3] = PACntrlReg[3];
    PACntrl[4] = PACntrlReg[4];
    PACntrl[5] = PACntrlReg[5];
    PACntrl[6] = PACntrlReg[6] & BCREnable;
    PACntrl[7] = PACntrlReg[7] & BCREnable;
    PACntrl[8] = NextPAStall;
    PACntrl[12:9] = PADFCCntrl;
    PACntrl[18:16] = PAOpCntrl;
end


// IO write control
always @(ExecuteReg or IOins)
    IOWCntrlDec = {~ExecuteReg[15],ExecuteReg[7],IOins};

// MMR write control
always @(ExecuteReg or MMRins)
    MMRWCntrlDec = {~ExecuteReg[15],ExecuteReg[7],MMRins};

// Two cycle instructions read control
always @(InsCycle or OpCntrlReg or OpReg or TwoCycRd)
    if (InsCycle)
        TwoCycRdDec = {OpCntrlReg[16] & (OpReg[10] | ~OpReg[9]),
          (OpCntrlReg[15] | (OpCntrlReg[16] & ~OpReg[10] & OpReg[9])) & OpReg[7],
          (OpCntrlReg[16] & (OpReg[11] | (OpReg[9] & ~OpReg[10]))) | OpCntrlReg[15]};
    else
        TwoCycRdDec = TwoCycRd;

// Suppress Data read
always @(LdDPStallDec or LdSTStallDec or RPTStallDec or LARStallDec  or
         OpCntrlReg or BlkMovStallDec or NextRPTCZero or InsCycle)
   DRSupp = ((LdDPStallDec | LdSTStallDec | RPTStallDec | LARStallDec | OpCntrlReg[13])
            & InsCycle)
            | (OpCntrlReg[19] & ((BlkMovStallDec & InsCycle) | ~NextRPTCZero));


// Auxillary update control
m3s086ct U3 (LdRPTCDat, LdRPTCPrg, LdRPTCEx, RptRegCntrl[0], RPTCZero,
  CycCntrlReg, Stall, PACntrl[9], RPTStall, ALUCntrlReg[11], NormEnab,
  NormAREnab, InsCycle, OpCntrlReg[18], OpCntrlReg[22], NLoSStall, DFCAuxStallReg,
  OpCntrlReg[14], LdSTStall, IOins, MMRins, OpReg[15:9], OpCntrlReg[0],
  RPTC, DataLatch, DataImm, ExecuteReg, DataBus, IndCntrlReg, IndpCntrlReg,
  IndsCntrlReg,
  SourceRPTCZero, DAAuxUpdate);

// ** Data address control **

// Data read address control (DACntrl[4:0])
always @(MadMacIns or BlkMovStall or RPTCZero or SourceRPTCZero or RPTCZero or
    BlkMovInsDec or BlkMovStallDec or FCycDec or IOins or MMRins or OpCntrlReg or
    MMRinsDec or IOinsDec or
    DRSupp or TwoCycRdDec or DRCntrlRegDec or DRpCntrlRegDec or PortRdCntrlDec)
begin
    if ((MadMacIns & (BlkMovStall | ~RPTCZero) & ~SourceRPTCZero) |
        (BlkMovInsDec & (BlkMovStallDec | ~SourceRPTCZero)))
        DACntrl[3:0] = {1'b0, TwoCycRdDec};
    else if (~DRSupp & (SourceRPTCZero |
        ((OpCntrlReg[22] | OpCntrlReg[18] | MMRins | IOins) & FCycDec)))
        DACntrl[3:0] = DRCntrlRegDec;
    else if (((MMRins | IOins) & ~RPTCZero) | DRSupp)
        DACntrl[3:0] = 4'b0;
    else DACntrl[3:0] = DRpCntrlRegDec;
    DACntrl[4] = PortRdCntrlDec;
end

// Data write address control (DACntrl[10:5])
always @(IOWCntrlDec or FCycDec or MMRWCntrlDec or BlkMovStallDec or BlkMovPADec
    or BlkMovWrDFCDec or OpCntrlReg or OpReg or PortWrCntrlDec or DWCntrlRegDec)
begin
    if (IOWCntrlDec[0] & ~FCycDec)
        DACntrl[10:5] = {1'b0,PortWrCntrlDec,1'b0,IOWCntrlDec};
    else if (MMRWCntrlDec[0] & ~FCycDec)
        DACntrl[10:5] = {2'b00,~MMRWCntrlDec[2],MMRWCntrlDec};
    else if (IOWCntrlDec[0] | MMRWCntrlDec[0])
        DACntrl[10:5] = 5'b0;
    else if (~(BlkMovStallDec | (BlkMovPADec & BlkMovWrDFCDec)
            | ((OpCntrlReg[22] | OpCntrlReg[18]) & OpReg[15] & FCycDec)))
        DACntrl[10:5] = {DWCntrlRegDec[4],1'b0,DWCntrlRegDec[3:0]};
    else DACntrl[10:5] = 5'b0;
end

// Auxillary register update stall
always @(DFCOp or RPTStall or RPTCZero or SourceRPTCZero or OpCntrlReg
    or TBLRStall or BlkMovWrDFC or LARStall)
begin
    DFCAuxStall = DFCOp & ~OpCntrlReg[22] & RPTCZero
       & (~SourceRPTCZero | (OpCntrlReg[15] & ~BlkMovWrDFC));
    AuxStall = (DFCAuxStall & ~LARStall) | RPTStall | TBLRStall;
end

// Auxillary register update control
always @(RPTCZero or SourceRPTCZero
    or ExCntrlReg or InstructReg or OpReg or ExecuteReg or AuxCntrlReg
    or MMRins or AuxStall or OpCntrlReg or DFCAuxStallReg
    or FCycDec or IOAccessDec or NLoSStall or DAAuxUpdate)
begin
    DACntrl[16:11] = AuxCntrlReg;
    if (((SourceRPTCZero & RPTCZero) | (ExCntrlReg[6] & ~MMRins)) &
         ~(OpCntrlReg[18] | OpCntrlReg[22]) & NLoSStall & ~DFCAuxStallReg)
        DAAuxCntrl = {InstructReg[10:8],InstructReg[2:0]};
    else if ((SourceRPTCZero & ~FCycDec) | RPTCZero)
        DAAuxCntrl = {OpReg[10:8],OpReg[2:0]};
    else DAAuxCntrl = {ExecuteReg[10:8],ExecuteReg[2:0]};
    DACntrl[32:17] = {AuxStall,DAAuxCntrl,DAAuxUpdate};
    DACntrl[33] = IOAccessDec;
end

// Direct addressing outputs
always @(NextRPTCZero or MMRinsDec or IOinsDec or NoUpdate
    or BlkMovInsDec or BlkMovStallDec or InsCycle
    or InstructReg or OpReg or ExecuteReg or IntVect or NextIntrEx)
begin
    if (NextRPTCZero & ~(MMRinsDec | IOinsDec | (BlkMovInsDec & BlkMovStallDec)))
    begin
        if (InsCycle)
            RdDirAddr = InstructReg[6:0];
        else
            RdDirAddr = OpReg[6:0];
    end
    else
    begin
        if (InsCycle)
            RdDirAddr = OpReg[6:0];
        else
            RdDirAddr = ExecuteReg[6:0];
    end
    if (InsCycle & ~NoUpdate)
    begin
        WrDirAddr[6:5] = OpReg[6:5];
        if (NextIntrEx)
            WrDirAddr[4:0] = IntVect;
        else
            WrDirAddr[4:0] = OpReg[4:0];
    end
    else
    begin
        WrDirAddr[6:5] = ExecuteReg[6:5];
        if (NextIntrEx)
            WrDirAddr[4:0] = IntVect;
        else
            WrDirAddr[4:0] = ExecuteReg[4:0];
    end
end

// Auxillary register short immediate data
always @(RPTCZero or LARStall or InstructReg or OpReg)
    if (RPTCZero & ~LARStall) ARImm = InstructReg[7:0];
    else ARImm = OpReg[7:0];

// Context Save
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        ContextSave <= 0;
        ContextRestore <= 0;
    end
    else if (AdvPipe)
    begin
        if (OpCntrlReg[6]) ContextSave <= 1;
        else ContextSave <= 0;
        if (OpCntrlReg[2] & ~OpReg[14]) ContextRestore <= 1;
        else ContextRestore <= 0;
    end

// CALU reg control
always @(CALURegCntrlReg or BlkMovStall or LdWrDFC)
begin
    CALURegCntrl[14:9] = CALURegCntrlReg[14:9];
    CALURegCntrl[8] = CALURegCntrlReg[8] | LdWrDFC;
    CALURegCntrl[7:4] = CALURegCntrlReg[7:4];
    if (BlkMovStall)
        CALURegCntrl[3:0] = 4'b0;
    else
        CALURegCntrl[3:0] = CALURegCntrlReg[3:0];
end

// Program Bus short immediate value
always @(InsCycle or NoUpdate or OpReg or ProgImmHi)
    if (InsCycle & ~NoUpdate)
        NextProgImmHi = OpReg[15:8] & {8{OpReg[11]}};
    else
        NextProgImmHi = ProgImmHi;

// ProgBus output controls
always @(MadMacInsDec or PADFCCntrlDec or PAOpCntrlDec or ProgBusDec or AdvPipe
         or LARStall or LdDPStall or RPTStall or DFConPBDec or PBEnabOp
         or PBEnabImm or PACntrl)
begin
    ProgBusInUse = PACntrl[15] | (PADFCCntrlDec[1] & DFConPBDec);
    NextPBEnabLatch = MadMacInsDec & ~ProgBusInUse;
    if (AdvPipe | LARStall)
        NextPBEnabOp = (ProgBusDec[0] | ProgBusDec[2]) &
            ~(ProgBusInUse | NextPBEnabLatch);
    else
        NextPBEnabOp = PBEnabOp & ~(ProgBusInUse | NextPBEnabLatch);
    if (AdvPipe | LARStall | LdDPStall | RPTStall)
        NextPBEnabImm = ProgBusDec[1] & ~(ProgBusInUse | NextPBEnabLatch);
    else
        NextPBEnabImm = PBEnabImm & ~(ProgBusInUse | NextPBEnabLatch);
    NextPBEnabIns = ~(NextPBEnabLatch | NextPBEnabOp | NextPBEnabImm | ProgBusInUse);
end

always @(posedge Clock or posedge Reset)
if (Reset)
begin
    PBEnabHi <= 1;
    PBEnabLo <= 1;
    PBEnabIns <= 1;
    PBEnabLatch <= 0;
    PBEnabOp <= 0;
    PBEnabImm <= 0;
end
else if (MemCycle)
begin
    PBEnabHi <= NextPBEnabIns | NextPBEnabLatch | NextPBEnabOp | NextPBEnabImm;
    PBEnabLo <= NextPBEnabIns | NextPBEnabLatch | NextPBEnabOp | NextPBEnabImm;
    PBEnabIns <= NextPBEnabIns;
    PBEnabLatch <= NextPBEnabLatch;
    PBEnabOp <= NextPBEnabOp;
    PBEnabImm <= NextPBEnabImm;
end

// Data Bus short immediate value
always @(ExecuteReg)
begin
    DataImm[7:0] = ExecuteReg[7:0];
    if (ExecuteReg[15] & ExecuteReg[14])
        DataImm[15:8] = {ExecuteReg[12],ExecuteReg[12],ExecuteReg[12],ExecuteReg[12:8]};
    else
        DataImm[15:8] = 8'b0;
end

// DataWrite output controls
always @(posedge Clock or posedge Reset)
if (Reset)
    PrgToData <= 0;
else if (AdvPipe)
    PrgToData <= OpCntrlReg[20];

always @(InsCycle or OpReg or PAOpCntrlDec or DBEnabImm)
begin
    if (InsCycle)
       NextDBEnabImm = ((OpReg[15:10] == 6'b101110) || (OpReg[15:13] == 3'b110));
    else
       NextDBEnabImm = DBEnabImm;
    NextDBEnabLatch = ~(PAOpCntrlDec[0] | NextDBEnabImm);
end

always @(BlkMovInsDec or DACntrl or OpCntrlReg or InsCycle or FCycDec
      or MMRAccessDec or IOAccessDec or StAccDec or LdWrDFCDec or PrgToData)
begin
    NextDWEnabLatch = (BlkMovInsDec | DACntrl[10] |
        (OpCntrlReg[20] & InsCycle) | (PrgToData & ~InsCycle) |
         ((MMRAccessDec | IOAccessDec) & ~FCycDec))
         & ~(StAccDec & InsCycle) & ~LdWrDFCDec;
end

always @(posedge Clock or posedge Reset)
if (Reset)
begin
    DBEnabHi <= 0;
    DBEnabLo <= 0;
    DBEnabImm <= 0;
    DBEnabLatch <= 0;
    DWEnabLatch <= 0;
end
else if (MemCycle)
begin
    DBEnabHi <= NextDBEnabImm | NextDBEnabLatch;
    DBEnabLo <= NextDBEnabImm | NextDBEnabLatch;
    DBEnabImm <= NextDBEnabImm;
    DBEnabLatch <= NextDBEnabLatch;
    DWEnabLatch <= NextDWEnabLatch;
end

// External interrupt acknowledge
always @(posedge Clock or posedge Reset)
    if (Reset) AckEnab <= 0;
    else AckEnab <= (ExCntrlReg[8] | IntrEx) & PACntrl[2];
always @(AckEnab or Clock)
    NIACK = ~(~Clock & AckEnab);

// DataWrite output mux
always @(DWEnabLatch or DataLatch or RPTC)
    if (DWEnabLatch) DataWriteOp = DataLatch;
    else DataWriteOp = RPTC;

// ProgBus output mux
always @(PBEnabLatch or PBEnabIns or PBEnabOp or PBEnabImm or
        ProgLatch or PBInsReg or PBOpReg or ProgImmHi or ExecuteReg)
    if (PBEnabIns) ProgBusOp <= PBInsReg;
    else if (PBEnabLatch) ProgBusOp <= ProgLatch;
    else if (PBEnabOp) ProgBusOp <= PBOpReg;
    else if (PBEnabImm) ProgBusOp <= {ProgImmHi,ExecuteReg[7:0]};
    else ProgBusOp <= 0;

// DataBus output mux
always @(DBEnabLatch or DBEnabImm or DataLatch or DataImm)
    if (DBEnabLatch) DataBusOp = DataLatch;
    else if (DBEnabImm) DataBusOp = DataImm;
    else DataBusOp = 0;

// Bus outputs
assign ProgBus[15:8] = (PBEnabHi) ? ProgBusOp[15:8] : 8'bZ;
assign ProgBus[7:0]  = (PBEnabLo) ? ProgBusOp[7:0] : 8'bZ;
assign DataBus[15:8] = (DBEnabHi) ? DataBusOp[15:8] : 8'bZ;
assign DataBus[7:0]  = (DBEnabLo) ? DataBusOp[7:0] : 8'bZ;
assign DataReadBus = (RptRegCntrl[1] & ~MMRAccess) ? RPTC : 16'bZ;
assign DataWrite = ((DWEnabLatch | (RptRegCntrl[1] & MMRAccess)) & ~BusReqMode)
     ? DataWriteOp : 16'bZ;

endmodule