m3s002ct.v

这是16位定点dsp源代码。已仿真和综合过了

            else LdRPTCEx <= 1'b0;
            DFCOp <= DFCProg | DFCReg | DFCWr;
        end
    end

always @(RPTC or LdRPTCDat or LdRPTCPrg or LdRPTCEx or RPTCZero or RptRegCntrl or
        CycCntrlReg or Stall or DataLatch or DataImm or ExecuteReg or
        DataBus or InsCycle or PACntrl or SourceRPTCZero)
begin
    LdRPTCDec = (~RPTCZero & ~CycCntrlReg & ~Stall & ~PACntrl[9])
        & ~(LdRPTCDat | LdRPTCPrg | LdRPTCEx | RptRegCntrl[0]);
    LdRPTCDef = ~(LdRPTCDat | LdRPTCPrg | LdRPTCEx | RptRegCntrl[0] | LdRPTCDec);
    SourceRPTC = (DataLatch  & {16{LdRPTCDat}}) |
                 (DataImm    & {16{LdRPTCPrg}}) |
                 (ExecuteReg & {16{LdRPTCEx}}) |
                 (DataBus    & {16{RptRegCntrl[0]}}) |
                 ((RPTC - 1) & {16{LdRPTCDec}}) |
                 (RPTC       & {16{LdRPTCDef}});
    if (~InsCycle & (LdRPTCDat | LdRPTCPrg | LdRPTCEx))
    begin
        NextRPTC = RPTC;
        NextRPTCZero = RPTCZero;
    end
    else
    begin
        NextRPTC = SourceRPTC;
        NextRPTCZero = SourceRPTCZero;
    end
end

// Pipeline stuffing
// Extend pipeline stuffing disable if wait-states are enabled
always @(posedge Clock or posedge Reset)
if (Reset)
    StuffEnabDel <= 0;
else if (AdvPipe)
    StuffEnabDel <= StuffEnab;

// Stuff INTR if IntReq or if previous instruction was IDLE/IDLE2 and INTM=0
always @(ProgReadBus or IntReq or IdleDec or IntVect or StuffEnab or INTM
    or ClrcIntmDec or PAStall or AdvPipe or MemCycle or StuffEnabDel)
begin
    IntrStuff = (IntReq & StuffEnab & (MemCycle | StuffEnabDel)) & ~PAStall;
    IntrStuffi = (IntReq & StuffEnab & (MemCycle | StuffEnabDel)) |
                 ((IdleDec & AdvPipe & (~INTM | ClrcIntmDec)) & ~PAStall);
    if (IntrStuffi)
        PipelineIp = {`C_INTR,IntVect};
    else
        PipelineIp = ProgReadBus;
end
always @(InsCycle or IntrOp or IntrEx)
    if (InsCycle)
        NextIntrEx = IntrOp;
    else
        NextIntrEx = IntrEx;

always @(LARStallDec or LdSTStallDec or InsCycle)
    NLoSStallDec = ~((LARStallDec | LdSTStallDec) & InsCycle);

// Pipeline stall registers
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        BlkMovStall <= 0;
        LdDPStall <= 0;
        LdSTStall <= 0;
        RPTStall <= 0;
        LARStall <= 0;
        BCRStall <= 0;
        TBLRStall <= 0;
        NLoSStall <= 0;
    end
    else if (MemCycle)
    begin
        BlkMovStall <= BlkMovStallDec;
        LdDPStall <= LdDPStallDec & InsCycle;
        LdSTStall <= LdSTStallDec & InsCycle;
        RPTStall <= RPTStallDec & InsCycle;
        LARStall <= LARStallDec & InsCycle;
        BCRStall <= OpCntrlReg[13] & InsCycle;
        TBLRStall <= TBLRStallDec;
        NLoSStall <= NLoSStallDec;
    end

// Suppress Execute register update for two cycle instructions
always @(RPTCZero or CycCntrlReg or IOins or MMRins)
    NoUpdate = ~RPTCZero | CycCntrlReg | IOins | MMRins;

// Pipeline input control
always @(InsCycle or OpCntrlReg or ExCntrlReg)
begin
    LdInsRegIp = InsCycle & ~(OpCntrlReg[2] & ~OpCntrlReg[12]);
    LdInsRegLtch = (InsCycle & ~(OpCntrlReg[2] & ~OpCntrlReg[12])) |
            (ExCntrlReg[7] & ~ExCntrlReg[5]);
end

// Instruction pipeline register muxes
always @(InsCycle or NoUpdate or InstructReg or OpReg or ExecuteReg)
begin
    if (InsCycle)
        NextOpReg = InstructReg;
    else
        NextOpReg = OpReg;
    if (InsCycle & ~NoUpdate)
            NextExecuteReg = OpReg;
        else
            NextExecuteReg = ExecuteReg;
end

// Indirect control register muxes
always @(InsCycle or NextRPTCZero or RPTCZero or LdRPTCDat or LdRPTCPrg or LdRPTCEx
  or IndCntrlReg or IndpCntrlReg or IndsCntrlReg)
begin
    if (InsCycle & NextRPTCZero & ~(LdRPTCDat | LdRPTCPrg | LdRPTCEx))
        NextIndpCntrlReg = IndCntrlReg;
    else
        NextIndpCntrlReg = IndpCntrlReg;
    if (RPTCZero & ~NextRPTCZero)
        NextIndsCntrlReg = IndCntrlReg;
    else
        NextIndsCntrlReg = IndsCntrlReg;
end

// Critical registers
m3s050ct U2 (Clock, Reset, MemCycle, IntrStuffi, ProgValid,
  LdInsRegIp, LdInsRegLtch, PipelineIp, InstructLatch,
  NextOpReg, NextExecuteReg, NextIndpCntrlReg, NextIndsCntrlReg, NextProgImmHi,
  NextDataLatch,
  InstructReg, OpReg, ExecuteReg, IndpCntrlReg, IndsCntrlReg, ProgImmHi,
  PBInsReg, PBOpReg, DataLatch);

// Control registers
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        CycCntrlReg <= 0;
        InstructLatch <= 0;
        ProgLatch <= 0;
        BlkMovPB <= 0;
        BlkMovPA <= 0;
        BlkMovRdDFC <= 0;
        BlkMovWrDFC <= 0;
        PLUCmpr <= 0;
        LdTBLW <= 0;
        iTBLW <= 0;
        IOins <= 0;
        IOAccess <= 0;
        PortRdCntrl <= 0;
        PortWrCntrl <= 0;
        IORead <= 0;
        IOWrite <= 0;
        MMRins <= 0;
        MadMacIns <= 0;
        BlkMovIns <= 0;
        MMRAccess <= 0;
        MMRRead <= 0;
        RptOut <= 0;
        NewPortAddr <= 0;
        IntrIns <= 0;
        IntrOp <= 0;
        IntrEx <= 0;
        ClrIntm <= 0;
        SetIntm <= 0;
        PrgWrEnab <= 0;
        LdARTC <= 0;
        LdARTC1 <= 0;
        NormAREnab <= 0;
        TwoCycRd <= 0;
    end
    else
    begin
        if (MemCycle)
        begin
            CycCntrlReg <= FCycDec;
            IntrEx <= NextIntrEx;
            NewPortAddr <= LdPortAddr;
            LdTBLW <= OpCntrlReg[17] & AdvPipe;
            iTBLW <= iTBLWDec;
            LdARTC1 <= DACntrl[19];
            LdARTC <= LdARTC1;
            PrgWrEnab <= NextPrgWrEnab;
            IOWrite <= (NewPortAddr & ~ExecuteReg[15]) | (IOWrite & (~RPTCZero | CycCntrlReg));
            IOAccess <= IOAccessDec;
            MMRAccess <= MMRAccessDec;
            RptOut <= IOins & ~RPTCZero;
            PortRdCntrl <= PortRdCntrlDec;
            PortWrCntrl <= PortWrCntrlDec;
            MadMacIns <= MadMacInsDec;
            BlkMovIns <= BlkMovInsDec;
            BlkMovPB <= BlkMovPBDec;
            BlkMovPA <= BlkMovPADec;
            BlkMovRdDFC <= BlkMovRdDFCDec;
            BlkMovWrDFC <= BlkMovWrDFCDec & ~BlkMovWrDFC;
            IOins <= IOinsDec;
            MMRins <= MMRinsDec;
            IORead <= IOReadDec;
            MMRRead <= MMRReadDec;
            TwoCycRd <= TwoCycRdDec;
        end
        if (AdvPipe)
        begin
            IntrOp <= IntrIns;
            ClrIntm <= OpCntrlReg[2] & ~OpReg[14] & OpReg[1];
            SetIntm <= OpCntrlReg[6];
            PLUCmpr <= OpCntrlReg[3];
        end
        if (ProgValid)
            InstructLatch <= PipelineIp;
        IntrIns <= IntrStuffi | (IntrIns & ~AdvPipe);
        if (MadMacEnab & ProgValid) ProgLatch <= ProgReadBus;
        if (ALUCntrlReg[11] & NormEnab & ~MemCycle) NormAREnab <= 1;
        else if (MemCycle) NormAREnab <= 0;
    end

// Port control
always@ (InsCycle or RPTCZero or CycCntrlReg or IORead or IOWrite or OpCntrlReg
     or PortRdCntrl or PortWrCntrl or IOAccess)
begin
    LdPortAddr = OpCntrlReg[18];
    if (PortRdCntrl)
        PortRdCntrlDec = ~InsCycle;
    else
        PortRdCntrlDec = ~RPTCZero & ~CycCntrlReg & IORead;
    if (PortWrCntrl)
        PortWrCntrlDec = ~InsCycle | CycCntrlReg;
    else
        PortWrCntrlDec = ~RPTCZero & ~CycCntrlReg & IOWrite;
    if (InsCycle & ~CycCntrlReg)
        IOAccessDec = OpCntrlReg[18];
    else
        IOAccessDec = IOAccess;
end

// MMR instruction
always @(InsCycle or CycCntrlReg or OpCntrlReg or MMRAccess)
begin
    if (InsCycle & ~CycCntrlReg)
        MMRAccessDec = OpCntrlReg[22];
    else
        MMRAccessDec = MMRAccess;
end

// TBLW instruction
always @(LdTBLW or iTBLW or RPTCZero)
    iTBLWDec = LdTBLW | (iTBLW & ~RPTCZero);

// MadMac/BlkMov instruction decode
always @(InsCycle or BCRStall or OpCntrlReg or OpReg or MadMacIns or BlkMovIns)
begin
    if (InsCycle | BCRStall)
    begin
        BlkMovInsDec = OpCntrlReg[15] | (OpCntrlReg[16] & ~(OpReg[10:9] == 2'b01));
        MadMacInsDec = OpCntrlReg[19];
    end
    else
    begin
        BlkMovInsDec = BlkMovIns;
        MadMacInsDec = MadMacIns;
    end
end

// DFC Control decode
always @(LdPrgDFC or LdRegDFC or LdWrDFC or DFConPA or SourceRPTCZero
     or BlkMovPA or BlkMovPB or DFConPB or InsCycle)
begin
    if (InsCycle | SourceRPTCZero)
    begin
        BlkMovPADec = (LdWrDFC | LdRegDFC | LdPrgDFC) & DFConPA;
        BlkMovPBDec = (LdPrgDFC | LdRegDFC) & DFConPB & InsCycle;
    end
    else
    begin
        BlkMovPADec = BlkMovPA;
        BlkMovPBDec = BlkMovPB;
    end
end

// DFC Control decode
always @(OpCntrlReg or InsCycle or BlkMovWrDFC or BlkMovRdDFC)
begin
    if (InsCycle)
    begin
        BlkMovRdDFCDec = OpCntrlReg[16];
        BlkMovWrDFCDec = OpCntrlReg[15];
    end
    else
    begin
        BlkMovRdDFCDec = BlkMovRdDFC;
        BlkMovWrDFCDec = BlkMovWrDFC;
    end
end

// MMR/IO instruction decode
always @(InsCycle or OpCntrlReg or OpReg or MMRins or IOins or MMRRead or IORead)
    if (InsCycle)
    begin
        MMRinsDec = OpCntrlReg[22];
        IOinsDec = OpCntrlReg[18];
        MMRReadDec = OpCntrlReg[22] & OpReg[15];
        IOReadDec = OpCntrlReg[18] & OpReg[15];
    end
    else
    begin
        MMRinsDec = MMRins;
        IOinsDec = IOins;
        MMRReadDec = MMRRead;
        IOReadDec = IORead;
    end

// Cycle control decode
always @(RPTCZero or CycCntrlReg or InsCycle or OpCntrlReg or MMRins or IOins)
    if (RPTCZero)
        FCycDec = (OpCntrlReg[22] | OpCntrlReg[18]) & ~CycCntrlReg & InsCycle;
    else
        FCycDec = (MMRins | IOins) & ~CycCntrlReg;

// Instruction decode block
m3s017ct U1 (Clock, Reset, AdvPipe, MemCycle, InsCycle, FCycDec,
        ARZ, LatchedNBIO, TC, AccNZ, AccLZ, OV, C,
        RPTCZero, InstructReg, OpReg, ExecuteReg, IntrIns, IntrOp,
        BlkMovStall, LdDPStall, LdSTStall, LARStall, BCRStall, TBLRStall,
	Stall, CycCntrlReg, MMRins, IOins, OpCntrlReg, ExCntrlReg,
        DRCntrlRegDec, DRpCntrlRegDec, DWCntrlRegDec, LdCntrlReg,
        AuxCntrlReg, IndCntrlReg, PLUCntrlReg, ProgBusDec, MultCntrl, ClrOV, BitTestEnab,
        DFCReg, DFCProg, DFCWr, ClrcIntmDec, StAccDec, MadMacDec, BCRDec,
        BCREnable, StuffEnab, IdleDec, iIdle, iIdle2, IFnEx,
        CALURegCntrlReg, CALUSelCntrl, ALUCntrlReg, SRCntrlReg, SetClrCntrl,
        BlkMovStallDec, LdDPStallDec, LdSTStallDec, RPTStallDec, LARStallDec,
        TBLRStallDec, RPTBDec, PopDec, PushDec, StackSelDec, PCSelDec, DPMovDec);

// Program address read stall
always @(SourceRPTCZero or NextStall or DFConPADec or BlkMovPADec or BlkMovRdDFCDec
       or MadMacInsDec or NextPrgWrEnab or iTBLWDec or TBLRStallDec)
    NextPAStall = ~((SourceRPTCZero & ~NextStall) |
              ((DFConPADec | BlkMovPADec) & BlkMovRdDFCDec) | MadMacInsDec) |
              NextPrgWrEnab | iTBLWDec | TBLRStallDec;

// Program write enable
always @(InsCycle or OpCntrlReg or RPTCZero or PrgWrEnab)
    NextPrgWrEnab = (OpCntrlReg[20] & InsCycle) | (PrgWrEnab & ~RPTCZero);


// ** Program address control **

// Program address control output
always @(BlkMovIns or MadMacIns or BlkMovStall or RPTCZero)
begin
    BlkMovEnab = BlkMovIns & (BlkMovStall | ~RPTCZero);
    MadMacEnab = MadMacIns & (BlkMovStall | ~RPTCZero);
end

// Pre decodes
always @(PopDec or AdvPipe or ExCntrlReg or BCRStall or BCREnable or PACntrlReg)
    if (AdvPipe | (ExCntrlReg[7] & BCREnable & BCRStall))
        NextPACntrl_7 = PopDec;
    else
        NextPACntrl_7 = PACntrlReg[7];

always @(LdPrgDFCDec or LdRegDFCDec or LdWrDFCDec or BlkMovPBDec or FCycDec
    or LARStallDec or RPTStallDec or OpCntrlReg or AdvPipe or InsCycle
    or RPTStall or LdPrgDFC or MadMacDec or OpReg or InstructReg
    or PADFCCntrl or LdDPStallDec or LdSTStallDec or NextRPTCZero or DPMovDec)
begin
    PADFCCntrlDec[0] = (LdPrgDFCDec & ~(BlkMovPBDec & ~LARStallDec)
                     & ~(RPTStallDec | LdDPStallDec | LdSTStallDec)
                     & NextRPTCZero)
                     | (LdPrgDFC & (RPTStall | LdDPStallDec | LdSTStallDec));
    PADFCCntrlDec[1] = (LdRegDFCDec & NextRPTCZero & ~(LdDPStallDec | LdSTStallDec))
                       | DPMovDec | (OpCntrlReg[20] & RPTStall);
    PADFCCntrlDec[2] = LdWrDFCDec;
    PADFCCntrlDec[3] = ~FCycDec & ~((((OpReg[15:12]==4'hA) && ~OpReg[11]) & NextRPTCZero & ~InsCycle)