m3s002ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Instruction Pipeline
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.121

// Revision history
// V1.121 - 15 May 1998
//          PADFCCntrlDec[3] modified to avoid incrementing DFC
//          when loading a BLPD address under certain circumstances.
// V1.120 - 23 April 1998
//          Interrupt stuffing delayed if wait-states enabled.
// V1.119 - 27 June 1997
//          Number of tr-state drivers reduced.
// V1.118 - 16 December 1996
//          IFnEx exported.
// V1.117 - 2 December 1996
//          DFCAuxStallReg exported.
// V1.116 - 20 November 1996
//          DataLatch only loaded on MemCycle.
// V1.115 - 25 October 1996
//          Disable AuxStall during LARStall.
// V1.114 - 17 October 1996
//          NextRPTCZero added to PADFCCntrlDec[3] and DFCWrCyc generation.
// V1.113 - 4 October 1996
//          NextRPTCZero added to PADFCCntrlDec[1] generation.
// V1.112 - 30 September 1996
//          OpCntrlReg[0] passed to m3s086ct.
// V1.111 - Incrementing of the DFC (PACntrl[12]),
//          BlkMovWrDFC assignment,
//          BlkMovPADec and BlkMovPBDec assignments modified to fix BLDD bug.

// m3s002ct
// M320C50 Pipeline and pipeline control
// Provides a four-stage instruction pipeline and a 16-bit repeat counter.
//
// Data enter the pipeline through the ProgReadBus and are latched into
// the InstructReg.
//
// On the next cycle the data are transfered to the OpReg, control signals
// are also decoded for the program and data access control blocks and
// latched into the OpCntrlReg.
//
// On the next cycle the data are transfered to the ExecuteReg, execution
// control signals are decoded and latched into the ExCntrlReg.
// The DataReadBus is latched into the DataReg to provide the DataBus.
// The ProgBus normally comes from the InstructReg.
//
// The InstructReg and DataReg are loaded once per pipeline cycle, when
// the ProgReady and DataReady become true respectively. The pipeline
// is only advanced when ProgReady, DataReady, and RPTCZero are true and
// Stall is false.
//
// The repeat counter is loaded from the DataBus then decrements every
// cycle that ProgReady and DataReady are true.
//
// CycleCntrlReg
//      0 : 1st cycle of 2 cycle instruction
//
// PACntrl usage:
//    2-0 : PC select lines
//    5-3 : Stack select lines
//      6 : Push stack
//      7 : Pop stack
//      8 : Disable address read
//      9 : Load DFC from ProgBus
//     10 : Load DFC from BMAR
//     11 : Load DFC from DataWrite
//     12 : Increment DFC
//     13 : Program write
//     14 : Enable DFC on ProgAddr
//     15 : Enable DFC on ProgBus
//     16 : Enable stack on DataBus
//     17 : Enable stack on DataWrite
//     18 : Load block repeat registers
//
// DACntrl usage:
//      0 : Read request
//      1 : Read indirect (1 = indirect, 0 = direct)
//      2 : Read immediate (1 = immediate)
//      3 : Read suppress data page
//      4 : Read from I/O address
//      5 : Write request
//      6 : Write indirect (1 = indirect, 0 = direct)
//      7 : Write immediate (1 = immediate)
//      8 : Write suppress data page
//      9 : Write to I/O address
//     10 : Write DMOV
//     11 : Load ST0
//     12 : Load ST1
//     13 : Read ST0
//     14 : Read ST1
//     15 : LAR from data bus
//     16 : LAR from prog bus
//     17 : Modify AR
//     18 : Load ARP
//     19 : Aux Reg compare with ARCR
//     20 : Short Immediate operand
//  24:21 : ARAU control
//     25 : Store Aux reg
//  28:26 : Next ARP / CM bits
//  31:29 : Aux reg store address
//     32 : Stall Aux register updates
//     33 : I/O Access

`define C_NOP 16'h8B00
`define C_INTR 11'b10111110011


module m3s002ct (ProgReadBus, DataReadBus, Clock, Reset, ContextSave, ContextRestore,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
        SpPmRdy, PrmRdy, ExPmRdy, SpDmRdy, ExDmRdy, MMRReady, BusReqMode,
        DpDataValid, SpDataValid, ExDataValid, MMDataValid, ProgValid,
        ARZ, NBIO, TC, AccNZ, AccLZ, OV, C, NormEnab, ClrOV, BitTestEnab,
        ProgBus, DataBus, RptRegCntrl,
        INTM, IntReq, IntVect, IntrStuff, IFnEx, IntrEx, ClrIntm, SetIntm,
        PACntrl, DACntrl, LdCntrlReg, PLUCntrlReg, MultCntrl, LdARTC,
        CALURegCntrl, CALUSelCntrl, ALUCntrlReg, SRCntrlReg, SetClrCntrl, PLUCmpr,
        iTBLWDec, LdPortAddr, MMRAccess, RptOut, iIdle, iIdle2,
        RdDirAddr, WrDirAddr, ARImm, DFCAuxStallReg,
        AdvPipe, InsCycle, AdvCycle, MemCycle, DataWrite, NIACK);
    input  [15:0] ProgReadBus;
    input         Clock, Reset, IntReq, INTM;
    input         SpPmRdy, PrmRdy, ExPmRdy, SpDmRdy, ExDmRdy, MMRReady;
    input         DpDataValid, SpDataValid, ExDataValid, MMDataValid, ProgValid;
    input         ARZ, NBIO, TC, AccNZ, AccLZ, OV, C, NormEnab, BusReqMode;
    input   [4:0] IntVect;
    input   [1:0] RptRegCntrl;
    inout  [15:0] DataWrite, DataReadBus;
    output [15:0] ProgBus, DataBus;
    output [18:0] PACntrl;
    output [33:0] DACntrl;
    output [1:0] LdCntrlReg;
    output [4:0] PLUCntrlReg;
    output [14:0] CALURegCntrl;
    output [9:0] CALUSelCntrl;
    output [11:0] ALUCntrlReg;
    output [6:0] SRCntrlReg;
    output [8:0] SetClrCntrl;
    output [6:0] RdDirAddr, WrDirAddr;
    output [7:0] ARImm;
    output       AdvPipe, InsCycle, AdvCycle, MemCycle, DFCAuxStallReg;
    output       ClrOV, BitTestEnab, PLUCmpr, iTBLWDec, LdPortAddr, MMRAccess;
    output       MultCntrl, ContextSave, ContextRestore, LdARTC, RptOut;
    output       IntrStuff, IFnEx, IntrEx, ClrIntm, SetIntm, iIdle, iIdle2, NIACK;

    tri  [15:0] ProgBus, DataBus, DataReadBus;
    reg  [15:0] NextDataLatch, ProgLatch, PipelineIp, InstructLatch;
    reg  [15:0] NextOpReg, NextExecuteReg;
    reg  [15:0] ProgBusOp, DataBusOp, DataWriteOp;
    wire [15:0] InstructReg, OpReg, ExecuteReg, PBInsReg, PBOpReg, DataLatch;
    reg   [6:0] RdDirAddr, WrDirAddr;
    reg  [18:0] PACntrl;
    reg  [33:0] DACntrl;
    reg   [8:0] NextIndpCntrlReg, NextIndsCntrlReg;
    wire  [8:0] IndpCntrlReg, IndsCntrlReg;
    reg  [15:0] DataImm;
    reg   [7:0] NextProgImmHi, ARImm;
    wire [22:0] OpCntrlReg;
    wire [8:0] ExCntrlReg;
    wire [3:0] DRCntrlRegDec, DRpCntrlRegDec;
    wire [4:0] DWCntrlRegDec;
    wire [1:0] LdCntrlReg;
    wire [5:0] AuxCntrlReg;
    wire [8:0] IndCntrlReg;
    wire [4:0] PLUCntrlReg;
    wire [2:0] ProgBusDec;
    wire [14:0] CALURegCntrlReg;
    wire [9:0] CALUSelCntrl;
    wire [11:0] ALUCntrlReg;
    wire [6:0] SRCntrlReg;
    wire [8:0] SetClrCntrl;
    wire [2:0] PCSelDec;
    wire [2:0] StackSelDec;
    wire [7:0] ProgImmHi;
    wire MultCntrl, ClrOV, BitTestEnab, IdleDec, iIdle, iIdle2;
    wire DFCReg, DFCProg, DFCWr;
    wire StuffEnab, ClrcIntmDec, StAccDec, MadMacDec;
    wire BlkMovStallDec, LdDPStallDec, LdSTStallDec, RPTStallDec, LARStallDec;
    wire TBLRStallDec;
    wire RPTBDec, PopDec, PushDec, BCRDec, BCREnable;
    reg BlkMovStall, LdDPStall, LdSTStall, RPTStall, LARStall;
    reg BCRStall, TBLRStall;
    reg AdvPipe, AdvCycle, MemCycle, CycCntrlReg, InsCycle;
    reg FCycDec, ContextSave, ContextRestore;
    reg [15:0] RPTC, SourceRPTC, NextRPTC;
    reg RPTCZero, NextRPTCZero, NextStall, Stall, DRSupp, RptOut;
    reg LoadData, LoadDataFromProg, LoadDataFromWrite, LdInsRegIp, LdInsRegLtch;
    reg LdRPTCDat, LdRPTCPrg, LdRPTCEx;
    reg LdPrgDFC, LdRegDFC, LdWrDFC, AuxStall, DFCAuxStall, DFCAuxStallReg;
    reg LdPrgDFCDec, LdRegDFCDec, LdWrDFCDec;
    reg [7:0] PACntrlReg;
    wire [8:0] DAAuxUpdate;
    reg [5:0] DAAuxCntrl;
    reg [2:0] TwoCycRdDec, TwoCycRd, IOWCntrlDec, MMRWCntrlDec;
    reg [14:0] CALURegCntrl;
    reg PLUCmpr, iTBLWDec, iTBLW, IOWrite, LdTBLW, LdARTC, LdARTC1;
    reg DFCWrCyc, DFConPB, DFConPADec, DFConPBDec, DFConPA;
    reg BlkMovPBDec, BlkMovPB, BlkMovPADec, BlkMovPA;
    reg BlkMovEnab, MadMacEnab, BlkMovRdDFCDec, BlkMovRdDFC, BlkMovWrDFCDec, BlkMovWrDFC;
    reg PBEnabLatch, PBEnabIns, PBEnabOp, PBEnabImm, PBEnabHi, PBEnabLo;
    reg NextPBEnabLatch, NextPBEnabIns, NextPBEnabOp, NextPBEnabImm;
    reg NextDBEnabLatch, NextDBEnabImm;
    reg DBEnabLatch, DBEnabImm, DBEnabHi, DBEnabLo;
    reg NextDWEnabLatch, DWEnabLatch;
    reg NextPAStall, PAStall, IntrStuff, IntrStuffi, IntrIns, IntrOp, NextIntrEx, IntrEx;
    reg ClrIntm, SetIntm, LdPortAddr, NewPortAddr;
    reg NIACK, AckEnab, NormAREnab, NLoSStallDec, NLoSStall;
    reg PortRdCntrlDec, PortRdCntrl, PortWrCntrlDec, PortWrCntrl;
    reg MMRAccessDec, MMRAccess, IOAccessDec, IOAccess;
    reg NextPrgWrEnab, PrgWrEnab, DFCOp;
    reg MadMacInsDec, MadMacIns, BlkMovInsDec, BlkMovIns;
    reg MMRinsDec, MMRins, IOinsDec, IOins, NoUpdate;
    reg MMRReadDec, MMRRead, IOReadDec, IORead;
    reg [3:0] PADFCCntrlDec, PADFCCntrl;
    reg [2:0] PAOpCntrlDec, PAOpCntrl;
    reg NextPACntrl_7, PrgToData, ProgBusInUse;
    reg LatchedNBIO, LdRPTCDec, LdRPTCDef;
    reg StuffEnabDel;
    wire SourceRPTCZero, IFnEx;

// Latch NBIO input signal
always @(posedge Clock)
    if (AdvPipe) LatchedNBIO <= NBIO;

// Pipeline stall control
always @(LARStallDec or BlkMovStallDec or LdDPStallDec or LdSTStallDec
    or RPTStallDec or OpCntrlReg or TBLRStallDec
    or iTBLWDec or NextPrgWrEnab or NextRPTCZero or InsCycle)
    NextStall = ((LARStallDec | LdDPStallDec | LdSTStallDec
        | RPTStallDec | OpCntrlReg[13] | TBLRStallDec) & InsCycle)
        | BlkMovStallDec | ((iTBLWDec | NextPrgWrEnab) & NextRPTCZero);
always @(posedge Clock or posedge Reset)
if (Reset)
    Stall <= 0;
else if (MemCycle)
    Stall <= NextStall;

// Pipeline control
always @(SpPmRdy or PrmRdy or ExPmRdy or SpDmRdy or ExDmRdy or MMRReady
    or DpDataValid or SpDataValid or ExDataValid or MMDataValid
    or RPTCZero or Stall or CycCntrlReg or LARStall or LdSTStall or ExCntrlReg)
begin
    MemCycle = SpPmRdy & PrmRdy & ExPmRdy & SpDmRdy & ExDmRdy & MMRReady;
    InsCycle = RPTCZero & ~Stall;
    AdvPipe = RPTCZero & MemCycle & ~Stall;
    LoadData = DpDataValid | (SpDataValid & SpDmRdy) |
             (ExDataValid & ExDmRdy) | (MMDataValid & MMRReady);
    AdvCycle = (RPTCZero & ~Stall) | (ExCntrlReg[7] & ~ExCntrlReg[5]) |
               LARStall | LdSTStall | ~RPTCZero;
end

// Data latch loads from program memory
always @(BlkMovPA or DFConPA or BlkMovRdDFC or BlkMovEnab or ProgValid)
    LoadDataFromProg = (BlkMovPA | DFConPA) & BlkMovRdDFC & BlkMovEnab & ProgValid;

// Data latch loads from DataWrite bus
always @(OpCntrlReg or OpReg)
    LoadDataFromWrite = OpCntrlReg[0] & (OpReg[15:8] == 8'h08);

// Data Latch
always @(LoadData or LoadDataFromProg or LoadDataFromWrite or
    DataReadBus or ProgReadBus or DataWrite or DataLatch)
    if (LoadData) NextDataLatch = DataReadBus;
    else if (LoadDataFromProg) NextDataLatch = ProgReadBus;
    else if (LoadDataFromWrite) NextDataLatch = DataWrite;
    else NextDataLatch = DataLatch;

// DFC load decodes
always @(InsCycle or DFCProg or DFCReg or DFCWrCyc or LdDPStallDec or LdSTStallDec or
    LdPrgDFC or LdRegDFC or LdWrDFC or InstructReg or DFConPA or DFConPB or RPTCZero)
begin
    if (InsCycle)
    begin
        LdPrgDFCDec = DFCProg;
        LdRegDFCDec = DFCReg;
    end
    else
    begin
        LdPrgDFCDec = LdPrgDFC;
        LdRegDFCDec = LdRegDFC;
    end
    LdWrDFCDec = InsCycle & DFCWrCyc & ~(LdDPStallDec | LdSTStallDec);
    if (InsCycle)
    begin
        DFConPADec = ((DFCReg | DFCProg) & ~(InstructReg[11] & ~InstructReg[9])) | DFCWrCyc;
        DFConPBDec = (DFCReg | DFCProg) & (InstructReg[11] & ~InstructReg[9]);
    end
    else
    begin
        DFConPADec = DFConPA;
        DFConPBDec = DFConPB;
    end
end

// Repeat Counter and DFC control
always @(posedge Clock or posedge Reset)
    if (Reset)
    begin
        DFCWrCyc <= 0;
        LdPrgDFC <= 0;
        LdRegDFC <= 0;
        LdWrDFC <= 0;
        RPTC <= 0;
        RPTCZero <= 1;
        LdRPTCDat <= 0;
        LdRPTCPrg <= 0;
        LdRPTCEx <= 0;
        DFConPB <= 0;
        DFConPA <= 0;
        DFCOp <= 0;
        DFCAuxStallReg <= 0;
    end
    else
    begin
        if (MemCycle) 
        begin
            LdPrgDFC <= LdPrgDFCDec;
            LdRegDFC <= LdRegDFCDec;
            LdWrDFC <= LdWrDFCDec;
            DFConPB <= DFConPBDec;
            DFConPA <= DFConPADec;
            DFCAuxStallReg <= DFCAuxStall;
            RPTC <= NextRPTC;
            RPTCZero <= NextRPTCZero;
        end
        if (AdvCycle & MemCycle & RPTCZero)
        begin
            DFCWrCyc <= DFCWr;
        end
        if (AdvPipe)
        begin
            if (OpCntrlReg[0] && (OpReg[15:8] == 8'h0B)) LdRPTCDat <= 1'b1;
            else LdRPTCDat <= 1'b0;
            if (OpCntrlReg[0] && (OpReg[15:8] == 8'hBB)) LdRPTCPrg <= 1'b1;
            else LdRPTCPrg <= 1'b0;
            if (ExCntrlReg[0] && (ExecuteReg[15:4] == 12'hBEC) && (ExecuteReg[3:1] == 3'b010))
                LdRPTCEx <= 1'b1;