m3s018ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Clock Control
// Copyright Mentor Graphics Corporation and licensors 1998.
// V1.102

// Revision history
// V1.102 - 22 July 1997
//          Latency in wakeup from idle mode reduced.
// V1.101 - 8 January 1997
//          DMA mode entry enabled during Idle modes.

// m3s018ct
// M320C50 Clock, power-down control and external interrupt synchronisation.
// Provides two clocks at half the frequency of FClock:
//    ClockCPU for the CPU
//    ClockPer for the peripherals
//
// ClockCPU is stopped by the IDLE instruction and
// by entering HOLD mode with HM=1. It is restarted by an unmasked interrupt,
// reset or the end of HOLD mode.
// ClockPer is stopped by the IDLE2 instruction. It is restarted by NINT1-4,
// NMI or a reset.
// ClockInt is the interrupt controller clock, it is active at the same time
// as ClockPer, the signal is kept seperate from ClockPer to allow the synthesizer
// to keep the clock skew between it and ClockCPU low.
//
// If the CPU clock is still running when DMA mode is entered, it will be stopped.
//
// The output signal IDLE2 will be high when the clock is stopped in idle2
// mode and can be used to disable the external clock generator.
//


module m3s018ct (NRS, NCLKI, NHOLD, HM, MemCycle, iIdle, iIdle2, NBRI, InsFetch,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    Wakeup, NNMI, NINT1, NINT2, NINT3, NINT4,
    Reset, FClock, CLKO, ClockCPU, ClockPer, ClockInt,
    ExtAccEnab, MemAccEnab, DMAMode, NHLDA, NHOE, NIAQ, IDLE2,
    NMISync, NInt1Sync, NInt2Sync, NInt3Sync, NInt4Sync);
    input     NRS, NCLKI, NHOLD, HM, MemCycle, iIdle, iIdle2, NBRI, InsFetch;
    input     Wakeup;
    input     NNMI, NINT1, NINT2, NINT3, NINT4;    
    output    Reset, FClock, CLKO, ClockCPU, ClockPer, ClockInt;
    output    ExtAccEnab, MemAccEnab, DMAMode, NHLDA, NHOE, NIAQ, IDLE2;
    output    NInt1Sync, NInt2Sync, NInt3Sync, NInt4Sync, NMISync;

    reg       Reset, FClock, CLKO, ClockSys, ClockCPU, ClockPer, ClockInt;
    reg [5:0] HoldSample;
    reg       CPUClockEnab, Holdl, Hold, HoldClockEnab, ExtAccEnab, MemAccEnab;
    reg       Idle1Mode, Idle2Mode, EndIdle, EndIdle2, IdleClockEnab, Idle2ClockEnab;
    reg [3:0] BRSample;
    reg       DMAMode, BRClockEnab, WakeupSync, CPUCyc;
    reg       IDLE2, NHLDA, NHOE, NIAQ;
    reg [4:0] NINT1Sample, NINT2Sample, NINT3Sample, NINT4Sample, NMISample;
    reg       NInt1Edge, NInt2Edge, NInt3Edge, NInt4Edge, NMIEdge;
    reg       NInt1Sync, NInt2Sync, NInt3Sync, NInt4Sync, NMISync;
    reg       NInt1Del, NInt2Del, NInt3Del, NInt4Del, NMIDel;
    reg       Int1s, Int2s, Int3s, Int4s, NMIs, EndIdle1;


// Input fast clock
always @(NCLKI)
    FClock = ~NCLKI;

// CPU clock enable
always @(HoldClockEnab or IdleClockEnab or BRClockEnab)
    CPUClockEnab = HoldClockEnab & IdleClockEnab & BRClockEnab;

// Reset and system clock generator
always @(posedge FClock or negedge NRS)
    if (~NRS)
    begin
        ClockSys <= 0;
        ClockCPU <= 0;
        ClockPer <= 0;
        ClockInt <= 0;
    end
    else
    begin
        ClockSys <= ~ClockSys;
        ClockCPU <= ~(ClockSys & CPUClockEnab); 
        ClockPer <= ~(ClockSys & Idle2ClockEnab);
        ClockInt <= ~(ClockSys & Idle2ClockEnab);
    end
always @(negedge ClockCPU or negedge NRS)
    if (~NRS) Reset <= 1;
    else Reset <= 0;
always @(ClockPer) CLKO = ~ClockPer;

// Hold mode control
// MemCycle sampled by ClockCPU to indicate end of memory access cycle.
// Sychronised to ClockSys by resampling on negative edge of ClockSys. 
always @(posedge ClockSys or posedge Reset)
    if (Reset)
    begin
        HoldSample[0] <= 0;
        HoldSample[2] <= 0;
        HoldSample[4] <= 0;
        HoldSample[5] <= 0;
    end
    else
    begin
        HoldSample[0] <= ~NHOLD;
        HoldSample[2] <= HoldSample[1];
        HoldSample[4] <= HoldSample[3];
        HoldSample[5] <= HoldSample[4];
    end
always @(negedge ClockSys or posedge Reset)
    if (Reset)
    begin
        HoldSample[1] <= 0;
        HoldSample[3] <= 0;
    end
    else
    begin
        HoldSample[1] <= HoldSample[0];
        HoldSample[3] <= HoldSample[1] & Hold;
    end
always @(posedge ClockCPU)
    CPUCyc <= MemCycle;
always @(posedge ClockSys)
    Holdl <=  HoldSample[1] | (Hold & ~HM & HoldSample[5]);
always @(Holdl or CPUCyc)
    Hold = CPUCyc | Holdl;

always @(HoldSample or Hold or HM)
begin
    NHLDA = ~(HoldSample[2] & HoldSample[4]);
    NHOE = HoldSample[3];
    HoldClockEnab = ~(Hold & (HoldSample[1] | HoldSample[5])) | ~HM;
    ExtAccEnab = ~(Hold & (HoldSample[1] | HoldSample[5]));
end

// Idle mode control
// Idle decodes and MemCycle sampled by ClockCPU.
// Idle mode ended by sampling; IntReq = 1 or NNMI/NINT on negative edge of ClockSys
// Synchronise wakeup signal
always @(posedge ClockSys or posedge Reset)
    if (Reset)
    begin
        WakeupSync <= 0;
        Idle1Mode <= 0;
        Idle2Mode <= 0;
    end
    else
    begin
        WakeupSync <= Wakeup;
        Idle1Mode <= ((iIdle | iIdle2) & ~Wakeup & MemCycle) | (Idle1Mode & ~EndIdle1);
        Idle2Mode <= (iIdle2 & ~Wakeup & MemCycle) | (Idle2Mode & ~EndIdle2);
    end
always @(negedge ClockSys or negedge NRS)
    if (~NRS)
    begin
        EndIdle <= 0;
        EndIdle1 <= 0;
        EndIdle2 <= 0;
    end
    else
    begin
        EndIdle <= WakeupSync & Idle1Mode;
	EndIdle1 <= EndIdle;
        EndIdle2 <= (NMIDel & ~NNMI)
                  | (NInt1Del & ~NINT1)
                  | (NInt2Del & ~NINT2)
                  | (NInt3Del & ~NINT3)
                  | (NInt4Del & ~NINT4);
    end
always @(Idle1Mode or EndIdle1)
    IdleClockEnab = ~(Idle1Mode & ~EndIdle1);
always @(Idle2Mode or EndIdle2)
begin
    IDLE2 = Idle2Mode & ~EndIdle2;
    Idle2ClockEnab = ~IDLE2;
end

// Disable memory access during idle modes
always @(Idle1Mode or Idle2Mode)
    MemAccEnab = ~(Idle1Mode | Idle2Mode);

// DMA mode control
// MemCycle sampled by ClockCPU to indicate end of memory access cycle.
// Sychronised to ClockSys by resampling on negative edge of ClockSys. 
always @(posedge ClockSys or posedge Reset)
    if (Reset)
        DMAMode <= 0;
    else
        DMAMode <= BRSample[1] & BRSample[3];
always @(posedge ClockSys)
        BRSample[0] <= ~NBRI & HoldSample[3];
always @(negedge ClockSys or negedge NRS)
    if (~NRS)
    begin
        BRSample[1] <= 0;
        BRSample[3] <= 0;
    end
    else
    begin
        BRSample[1] <= BRSample[0];
        BRSample[3] <= BRSample[1] & (BRSample[2] | ~CPUClockEnab);
    end
always @(posedge ClockCPU)
    BRSample[2] <= (BRSample[1] & (MemCycle | HoldSample[3]));
always @(BRSample or DMAMode)
    BRClockEnab = ~(BRSample[2] & (DMAMode | BRSample[1]));

// NIAQ signal
always @(InsFetch or DMAMode)
    NIAQ = ~(InsFetch | DMAMode);

// External interrupt synchronisation
always @(posedge ClockSys)
begin
    NINT1Sample[0] <= ~NINT1;
    NINT1Sample[1] <= NINT1Sample[0];
    NINT1Sample[2] <= NINT1Sample[1];
    NINT1Sample[3] <= ~NINT1Sample[2];
    NINT1Sample[4] <= NINT1Sample[3];
    NINT2Sample[0] <= ~NINT2;
    NINT2Sample[1] <= NINT2Sample[0];
    NINT2Sample[2] <= NINT2Sample[1];
    NINT2Sample[3] <= ~NINT2Sample[2];
    NINT2Sample[4] <= NINT2Sample[3];
    NINT3Sample[0] <= ~NINT3;
    NINT3Sample[1] <= NINT3Sample[0];
    NINT3Sample[2] <= NINT3Sample[1];
    NINT3Sample[3] <= ~NINT3Sample[2];
    NINT3Sample[4] <= NINT3Sample[3];
    NINT4Sample[0] <= ~NINT4;
    NINT4Sample[1] <= NINT4Sample[0];
    NINT4Sample[2] <= NINT4Sample[1];
    NINT4Sample[3] <= ~NINT4Sample[2];
    NINT4Sample[4] <= NINT4Sample[3];
    NMISample[0] <= ~NNMI;
    NMISample[1] <= NMISample[0];
    NMISample[2] <= NMISample[1];
    NMISample[3] <= ~NMISample[2];
    NMISample[4] <= NMISample[3];
    NInt1Del <= NInt1Edge & ~NINT1;
    NInt2Del <= NInt2Edge & ~NINT2;
    NInt3Del <= NInt3Edge & ~NINT3;
    NInt4Del <= NInt4Edge & ~NINT4;
    NMIDel <= NMIEdge & ~NNMI;
end
always @(NINT1Sample or Int1s)
    NInt1Edge = (NINT1Sample[0] & NINT1Sample[1] & NINT1Sample[2]
               & NINT1Sample[3] & NINT1Sample[4]);
always @(NInt1Edge or Int1s)
    NInt1Sync = NInt1Edge | Int1s;
always @(NINT2Sample or Int2s)
    NInt2Edge = (NINT2Sample[0] & NINT2Sample[1] & NINT2Sample[2]
               & NINT2Sample[3] & NINT2Sample[4]);
always @(NInt2Edge or Int2s)
    NInt2Sync = NInt2Edge | Int2s;
always @(NINT3Sample or Int3s)
    NInt3Edge = (NINT3Sample[0] & NINT3Sample[1] & NINT3Sample[2]
               & NINT3Sample[3] & NINT3Sample[4]);
always @(NInt3Edge or Int3s)
    NInt3Sync = NInt3Edge | Int3s;
always @(NINT4Sample or Int4s)
    NInt4Edge = (NINT4Sample[0] & NINT4Sample[1] & NINT4Sample[2]
               & NINT4Sample[3] & NINT4Sample[4]);
always @(NInt4Edge or Int4s)
    NInt4Sync = NInt4Edge | Int4s;
always @(NMISample or NMIs)
    NMIEdge = (NMISample[0] & NMISample[1] & NMISample[2]
             & NMISample[3] & NMISample[4]) | NMIs;
always @(NMIEdge or NMIs)
    NMISync = NMIEdge | NMIs;

// Stretch interrupts if coming out of idle2
always @(posedge ClockSys)
begin
    Int1s <= NInt1Sync & Idle2Mode;
    Int2s <= NInt2Sync & Idle2Mode;
    Int3s <= NInt3Sync & Idle2Mode;
    Int4s <= NInt4Sync & Idle2Mode;
    NMIs <= NMISync & Idle2Mode;
end

endmodule