m3s029ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// TDM Serial Port Transmitter
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.007

// m3s029ct
// M320C50 TDM serial port transmitter.
// Similar to Serial Port Transmitter except that in TDM mode it will only
// transmit if TxRegNotEmpty=1.
//
// TDX is the output data, NTDXE the enable xmit data line (low true)
// FSXI and FSXO are the Frame Synchronisation signals for transmit
// operation (input and output respectively)
// FO, FSM, TXM are control bits from the TSPC register
// TxRegNotEmpty is the transmit underflow flag for the control register
// TxRdy is the transmit ready flag
// XRST is the transmit reset line (low true)
// TXNT is the transmit interrupt
// Note for higher levels, the TXNT interrupt must be tested for as a
// transition from 0 to 1, not as a level.
// Also: the TxReset input must be driven at least 2 TxClock periods before the
// clocks stop
// Latencies: 	TDXR write to TDX out
//               min 2 TxClock
//               max 3 TxClock

// State machine definitions TSPC mode
`define C_SPCR_E_XSR_E 0
`define C_SPCR_F_XSR_E 1
`define C_SPCR_E_XSR_F 2
`define C_SPCR_F_XSR_F 3
// State machine definitions TDM mode
`define C_TDMR_E_XSR_E 4
`define C_TDMR_F_XSR_E 5
`define C_TDMR_E_XSR_F 6
`define C_TDMR_F_XSR_F 7

module m3s029ct (Clock, TxClock, NTxClock, TxReset, MMRWriteData, WriteTDXR,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
      TDM, FO, FSM, TXM, FSXI, FSXO, TDX, NTDXE, TxRegNotEmpty,
      TxRdy, NextTDXR, TXNT, TxCount, TxSlot, TCSRSave);

  input  [15:0] MMRWriteData;
  input         Clock, TxClock, NTxClock, TxReset, WriteTDXR;
  input         TDM, FO, FSM, TXM, FSXI;
  input  [7:0]  TCSRSave;

  output [15:0] NextTDXR;
  output        FSXO, TDX, NTDXE, TxRegNotEmpty, TXNT, TxRdy;
  output  [3:0] TxCount;
  output  [2:0] TxSlot;
  
  reg [15:0] TDXR, NextTDXR, XSR;
  reg        TxRegNotEmpty;
  reg  [3:0] TxCount;                    // transmit bit counter
  reg  [2:0] TxSlot, NextTxSlot;
  reg        NTDXE, NTTDXE, NTTDXED, LocalFSX, InternalFSX, SampleFSX;
  reg        TXNT, TxRdy, TxRdyReg, ClrTxRdy, TDX, LdXSRInt;
  reg        WrTDXRSync, WrTDXRSig;      // TDXR write strobe sync latches
  reg  [2:0] TxState;
  reg        FSXO, LastBit, L_Bit, TxRdyIp, Shift_XSR, TDMIp;

//
// TDXR register
//
always @(MMRWriteData or WriteTDXR or TDXR)
begin
    if (WriteTDXR) NextTDXR = MMRWriteData;
    else NextTDXR = TDXR;
end
always @(posedge Clock)
    TDXR <= NextTDXR;
always @(posedge Clock or negedge TxReset)
begin
    if (~TxReset) WrTDXRSig <= 1'b0;
    else begin 
        if (WriteTDXR) WrTDXRSig <= 1'b1;
        else WrTDXRSig <= !WrTDXRSync & WrTDXRSig;
    end
end
//
// synchronise WriteTDXR -> WrTDXRSync, 1 TxClock period.
// assumes WriteTDXR is less than 1 TxClock period long
//
always @(posedge TxClock or negedge TxReset)
begin
  if (~TxReset) WrTDXRSync <= 1'b0;
  else WrTDXRSync <= WrTDXRSig;
end
//
// transmit control state machine
//
always @(posedge NTxClock or negedge TxReset)
begin
    if (~TxReset)
        TxState <= 0;
    else
    case (TxState)
      `C_SPCR_E_XSR_E: if (WrTDXRSync)
                           TxState <= {TDM,2'b01}; // SPCR_F_XSR_E or TDMR_F_XSR_E

      `C_SPCR_F_XSR_E: TxState <= `C_SPCR_E_XSR_F;

      `C_SPCR_E_XSR_F: if (WrTDXRSync && !L_Bit) TxState <= `C_SPCR_F_XSR_F;
	               else if (WrTDXRSync && L_Bit) TxState <= `C_SPCR_E_XSR_F;
	                    else if (L_Bit) TxState <= `C_SPCR_E_XSR_E;

      `C_SPCR_F_XSR_F: if (L_Bit) TxState <= `C_SPCR_E_XSR_F;


      `C_TDMR_E_XSR_E: if (WrTDXRSync) TxState <= `C_TDMR_F_XSR_E;

      `C_TDMR_F_XSR_E: if (LocalFSX) TxState <= `C_TDMR_E_XSR_F;

      `C_TDMR_E_XSR_F: if (WrTDXRSync && !LocalFSX) TxState <= `C_TDMR_F_XSR_F;
	               else if (WrTDXRSync && LocalFSX) TxState <= `C_TDMR_E_XSR_F;
	                    else if (LastBit) TxState <= `C_TDMR_E_XSR_E;

      `C_TDMR_F_XSR_F: if (LocalFSX) TxState <= `C_TDMR_E_XSR_F;
                       else if (LastBit) TxState <= `C_TDMR_F_XSR_E;

       default: TxState <= TxState;

    endcase
end
//
// generate LastBit signal
//
always @(TxCount or NTTDXE)
begin
    LastBit = ((TxCount ==15) && !NTTDXE);
end
always @(posedge NTxClock)
begin
    L_Bit <= LastBit;
end
//
// generate shift control
//
always @(SampleFSX or NTTDXE or L_Bit)
begin
    Shift_XSR = (SampleFSX | (~NTTDXE & ~L_Bit));
end   
//
// TxRegNotEmpty flag synchronised
//
always @(posedge TxClock)
begin
    if (~TxReset) TxRegNotEmpty <= 0;    
    else if ((TxState == `C_SPCR_F_XSR_E)
            ||(TxState == `C_TDMR_F_XSR_E)) TxRegNotEmpty <= 1;
         else if (((TxState == `C_SPCR_E_XSR_F) || (TxState == `C_TDMR_E_XSR_F))
              && LastBit && !WrTDXRSync) TxRegNotEmpty <= 0;
end
//
// Transmit counter - counts 0,1,2,3,4,5,14,15 if FO == 1, 0 to 15 if FO == 0
//
always @(posedge NTxClock or negedge TxReset)
begin
    if (!TxReset) TxCount <= 4'b1110;    // asynchronous set
    else if (FSXI) TxCount <= 4'b0; // synchronous reset of counter
         else if (FO == 1 && TxCount == 5) TxCount <= 4'b1110 ;// FO controls 8/16 bit operation
	      else TxCount <= TxCount + 1;
end
//
// TxSlot counter
//
always @(posedge NTxClock or negedge TxReset)
begin
  if (~TxReset) TxSlot <= 0;
  else if (FSXI) TxSlot <=0;
       else if (TxCount == 15) TxSlot <= NextTxSlot;
end
always @(TxSlot)
begin
  NextTxSlot = TxSlot + 1;
end
//
// Output enable active
//
always @(posedge TxClock or negedge TxReset)
begin
  if (~TxReset) NTTDXE <= 1'b1;
  else NTTDXE <= (~(SampleFSX & TxRegNotEmpty) & (NTTDXE | L_Bit));
end
//
// Create 1/2 clock gap between differnet TX devices slots
//
always @(posedge NTxClock)
begin
   NTTDXED <= NTTDXE & TDM;
end
always @(NTTDXE or NTTDXED)
begin
  NTDXE = (NTTDXE | NTTDXED);
end
//
// Frame Sync control
// sample LocalFSX
//
always @(posedge NTxClock or negedge TxReset)
begin
    if (~TxReset) SampleFSX <= 0;
    else SampleFSX <= LocalFSX;
end
//
// internal FSX pulses
//
always @(posedge TxClock or negedge TxReset)
begin
    if (!TxReset) InternalFSX <= 0;
    else if ((TxState == `C_SPCR_F_XSR_E) && TXM) InternalFSX <= 1;
         else if ((TxState == `C_SPCR_F_XSR_F) && (TXM | ~FSM) && LastBit) InternalFSX <= 1;
              else InternalFSX <= 0;
end 
//   
// only output FSX pulses for first frame after idle if FSM is 0
//
always @(InternalFSX or NTDXE or FSM)
begin
    FSXO = (InternalFSX & (NTDXE | FSM)); 
end
//
// Combine internal and external FSX signals into signal LocalFSX
//
always @(TDM or TXM or FSM or InternalFSX or FSXI or TxRegNotEmpty or NTDXE or TxCount
         or NextTxSlot or TCSRSave)
begin
    if (TDM)            // in TDM mode transmit if TXDR not empty
    begin
        LocalFSX = ((TxCount == 15) && TCSRSave[NextTxSlot]);
    end
    else if (TXM)       // source FSX pulses internal or external
        LocalFSX = InternalFSX ;
    else if (FSM)       // Frame Sync mode always allows FSX pulses
        LocalFSX = FSXI ;
    else if (~NTDXE | TxRegNotEmpty) // allow aborts but no retransmit of old data
        LocalFSX = FSXI | InternalFSX;
    else
        LocalFSX = 0;   // disable if idle in continuous mode    
end
//
// XSR = transmit shift register
//
always @(posedge TxClock)
begin
    case (TxState) // NOTE: all states covered

      `C_SPCR_E_XSR_F: if (Shift_XSR) XSR <= {XSR[14:0],1'b0};  // shift

      `C_SPCR_F_XSR_F: if (LastBit) XSR <= TDXR ; // load shift register
                         else if (Shift_XSR) XSR <= {XSR[14:0],1'b0};  // shift


      `C_TDMR_E_XSR_F: XSR <= {XSR[14:0],1'b0};

      `C_TDMR_F_XSR_F: if (LastBit) XSR <= TDXR;
                       else XSR <= {XSR[14:0],1'b0};


        default: XSR <= TDXR ; // default load
    endcase
end
//
// output data synchronised to other edge
//
always @(posedge TxClock)
begin
    if (FO) TDX <= XSR[7];
    else TDX <= XSR[15];
end
//
// generate TxRdyIp signal on load of XSR
//
always @(TxState or LastBit or TxReset or TDMIp)
begin
    TxRdyIp = ((TxState == `C_SPCR_F_XSR_E)
       || ((TxState == `C_SPCR_F_XSR_F) && LastBit)
       || TDMIp
       || ~TxReset);
end
//
// generate TDM part of TxRdyIp & LdXSRInt
//
always @(posedge TxClock)
begin
  TDMIp <= (((TxState == `C_TDMR_F_XSR_E) && LocalFSX)
       || ((TxState == `C_TDMR_F_XSR_F) && LocalFSX));
end
//
// generate TxRdy clear signal from WriteTDXR
//
always @(posedge Clock or negedge TxReset)
begin
    if (~TxReset) ClrTxRdy <= 0;
    else ClrTxRdy <= (WriteTDXR | (ClrTxRdy & TxRdyReg));
end
//
// generate TxRdy signal
//
always @(posedge NTxClock or negedge TxReset)
begin
    if (~TxReset) TxRdyReg <= 1;
    else TxRdyReg <= TxRdyIp | (TxRdyReg & ~ClrTxRdy);
end
always @(TxRdyReg or ClrTxRdy or WriteTDXR)
begin
    TxRdy = TxRdyReg & ~(ClrTxRdy | WriteTDXR);
end
//
// generate transmit interrupts on TxRdy transition
//
always @(posedge TxClock)
begin
    LdXSRInt <= ((TxState == `C_SPCR_F_XSR_E)
       || ((TxState == `C_SPCR_F_XSR_F) && LastBit));
end

always @(posedge Clock or negedge TxReset)
begin
   if (~TxReset) TXNT <= 0;
   else TXNT <= LdXSRInt | TDMIp;
end

endmodule