m3s071ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Program Address Generator
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.202

// Revision history
// V1.202 - 16 December 1996
//          IFnEx passed to block repeat controller.
// V1.201 - 20 November 1996
//          Inputs for putting write data on ProgReadBus.
//          ProgRead tri-states replaced by a mux
// V1.2   - 3 June 1996
//          Tri-state buffers removed and module renamed as m3s071ct.
//          SetBRAF signal added, from m3s008ct.
// V1.105 - 10 May 1996

// m3s071ct
// M320C50 Program address generator and stack
// Provides the 16-bit program address for instruction and program data
// fetches, incorporating an 8-level stack, and a block repeat controller.
//
// The control lines PACntrl[2:0] select the next value for the prefetch counter
// as shown below:
//   000      PFC
//   001      PFC+1
//   010      TOS (Top of stack)
//   011      DataWrite (from lower half of the accumulator)
//   100      ProgBus
//   101      Vector (formed from IntPtr and IntNum)
//
// Control lines PACntrl[5:3] select the input data for the stack:
//   000      NewPFC (used for delayed call instructions)
//   001      PFCPrev1 (used for call instructions)
//   010      DataWrite (from lower half of the accumulator)
//   011      DataBus
//   100      PFCPrev2 (used for hardware interrupts)
//
// Control lines PACntrl[7:6] control the stack:
//     6    Push onto stack
//     7    Pop stack
//
// When PACntrl[8] is high no program read request is generated.
//
// Control lines PACntrl[12:9] control the DFC:
//     9    Load DFC from ProgBus
//    10    Load DFC from BMAR
//    11    Load DFC from DataWrite
//    12    Increment DFC
//
// When PACntrl[13] is high a program write occurs.
//
// Control lines PACntrl[17:14] enable output data:
//    14    Enable DFC onto PrgRdAddr
//    15    Enable DFC onto ProgBus
//    16    Enable the stack onto DataBus
//    17    Enable the stack onto DataWrite
// 
// When PACntrl[18] is high a block repeat operation is initiated.
//
// BMARRegCntrl:
//    0    Load BMAR from DataBus
//    1    Enable BMAR onto DataWrite
//
// The program prefetch counter (PFC) is used to address program space to
// read instructions.
// The data prefetch counter (DFC) is used to address program or data space to
// read data for instructions requiring two operands.
//
// The memory block being address is decoded and one of four memory request
// lines will go high. If CNF=1 the dual-port RAM block0 is enabled at FE00.
// If RAM=1 the single-port RAM is enabled at the address defined by the
// C_PR constant (in the file "m320c50.inc").
// If MPNMC=0 the internal program memory is enabled.

`include "m320c50.inc"

module m3s071ct (ProgBus, DataBus, IntPtr, IntNum, B0D, PD, DI,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    Clock, MemCycle, InsCycle, Reset, PACntrl, BMARRegCntrl, BrptRegCntrl, iMMR,
    MPNMC, CNF, RAM, BRAF, SetBRAF, ClrBRAF, iTBLW, DMAMode,
    PrProgValid, DpProgValid, SpProgValid, ExProgValid,
    SpRdWrDet, IFnEx,
    ProgAddr, DataWrite, PrDpReq, PrSpReq, PrPrReq, PrExReq,
    PwDpReq, PwSpReq, PwPrReq, PwExReq, ProgValid,
    DataRead, InsFetch, ProgRead, DFC, StackOut, NextBMAR, BMAR,
    DFCProgEnab, StackDataEnab, StackWriteEnab, BMARReadEnab, BMARProgEnab);

    input  [15:0] ProgBus, DataBus, DataWrite;
    input  [15:0] B0D, PD, DI;
    input   [4:0] IntPtr, IntNum;
    input         Clock, MemCycle, InsCycle, Reset;
    input  [18:0] PACntrl;
    input   [1:0] BMARRegCntrl;
    input   [5:0] BrptRegCntrl;
    input         MPNMC, CNF, RAM, BRAF, iTBLW, iMMR, DMAMode;
    input         PrProgValid, DpProgValid, SpProgValid, ExProgValid;
    input         SpRdWrDet, IFnEx;
    output [15:0] ProgAddr, DataRead, ProgRead;
    output        SetBRAF, ClrBRAF, ProgValid, InsFetch;
    output        PrDpReq, PrSpReq, PrPrReq, PrExReq;
    output        PwDpReq, PwSpReq, PwPrReq, PwExReq;
    output [15:0] DFC, StackOut, NextBMAR, BMAR;
    output        DFCProgEnab, StackDataEnab, StackWriteEnab;
    output        BMARReadEnab, BMARProgEnab;

    reg  [15:0] NextPFC, StackIn, PFCInc, PFCPrev1, PFCPrev2, Vector;
    reg  [15:0] NextDFC, DFCSource, NextProgAddr, ProgRead;
    reg  [15:0] NewPFC, NextBMAR;
    reg         NextPrDpReq, NextPrSpReq, NextPrPrReq, NextPrExReq;
    reg         NextPwDpReq, NextPwSpReq, NextPwPrReq, NextPwExReq;
    reg         ProgValid, InsFetch, StartCyc, ProgReadCyc;
    reg         AddrSourceSel, ProgBusEnab, ProgReadEnab;
    reg         DFCProgEnab, StackDataEnab, StackWriteEnab;
    reg         BMARReadEnab, BMARProgEnab;
    tri  [15:0] DataWrite, ProgBus, DataBus, StackOut;
    wire [15:0] PASR, PFC, DFC, BMAR, ProgAddr;
    wire        PrDpReq, PrSpReq, PrPrReq, PrExReq;
    wire        PwDpReq, PwSpReq, PwPrReq, PwExReq;
    wire        SelPASR, SetBRAF, ClrBRAF;

// Form interrupt vector
always @(IntPtr or IntNum)
    Vector = {IntPtr,5'b0,IntNum,1'b0};

// Block repeat multiplexer
always @(SelPASR or PASR or PFCInc)
    if (SelPASR) NewPFC = PASR;
    else NewPFC = PFCInc;

// Latch PACntrl [15:14]
always @(posedge Clock)
if (MemCycle)
begin
    AddrSourceSel <= PACntrl[14];
    ProgBusEnab <= PACntrl[15];
end

// Prefetch counter
always @(PACntrl or PFC or NewPFC or StackOut or DataWrite or ProgBus or Vector)
    case (PACntrl[2:0])
        3'b000 : NextPFC = PFC;
        3'b001 : NextPFC = NewPFC;
        3'b010 : NextPFC = StackOut;
        3'b011 : NextPFC = DataWrite;
        3'b100 : NextPFC = ProgBus;
        3'b101 : NextPFC = Vector;
        default : NextPFC = PFC;
    endcase

// Prefetch counter incrementer
always @(PFC)
   PFCInc = PFC+1;

// Data prefetch counter data source
always @(PACntrl or ProgBus or BMAR or DFC or DataWrite)
begin
    if (PACntrl[9]) DFCSource = ProgBus;
    else if (PACntrl[10]) DFCSource = BMAR;
    else if (PACntrl[11]) DFCSource = DataWrite;
    else DFCSource = DFC;
    if (PACntrl[12])
        NextDFC = DFCSource+1;
    else
        NextDFC = DFCSource;
end

// Stack input multiplexer
always @(NewPFC or PFCPrev1 or PFCPrev2 or DataWrite or DataBus or PACntrl)
    case (PACntrl[5:3])
        3'b000 : StackIn = NewPFC;
        3'b001 : StackIn = PFCPrev1;
        3'b010 : StackIn = DataWrite;
        3'b011 : StackIn = DataBus;
        default : StackIn = PFCPrev2;
    endcase

// Latches
m3s057ct U3 (Clock, MemCycle, Reset, NextPFC, NextDFC, NextBMAR, NextProgAddr,
  NextPrDpReq, NextPrSpReq, NextPrPrReq, NextPrExReq,
  NextPwDpReq, NextPwSpReq, NextPwPrReq, NextPwExReq,
  PFC, DFC, BMAR, ProgAddr,
  PrDpReq, PrSpReq, PrPrReq, PrExReq, PwDpReq, PwSpReq, PwPrReq, PwExReq);

// Previous address latches
always @(posedge Clock)
if (MemCycle & (PACntrl[0] | PACntrl[1] | PACntrl[2]))
begin
    PFCPrev1 <= PFC;
    PFCPrev2 <= PFCPrev1;
end

// Stack
m3s004ct U1 (StackIn, PACntrl[6], PACntrl[7], Clock, MemCycle, Reset, StackOut);

// Block repeat controller
m3s008ct U2 (ProgBus, DataBus, PFC, PFCPrev1,
    Clock, MemCycle, InsCycle, PACntrl[18], BrptRegCntrl, iMMR, BRAF, IFnEx,
    PASR, SelPASR, SetBRAF, ClrBRAF, DataWrite, DataRead);

// BMAR register
always @(MemCycle or BMARRegCntrl or iMMR or DataBus or DataWrite or BMAR)
    if (BMARRegCntrl[0] & iMMR) NextBMAR = DataBus;
    else if (BMARRegCntrl[0] & ~iMMR) NextBMAR = DataWrite;
    else NextBMAR = BMAR;

// Next program address multiplexer
always @(PACntrl or NextDFC or NextPFC or NextBMAR or ProgAddr)
if (~PACntrl[8] | PACntrl[13])
begin
    if (PACntrl[10] & PACntrl[14])
        NextProgAddr = NextBMAR;
    else if (PACntrl[14])
        NextProgAddr = NextDFC;
    else
        NextProgAddr = NextPFC;
end
else
    NextProgAddr = ProgAddr;

// Enable program reads
always @(PACntrl)
    ProgReadEnab = ~PACntrl[8];

// Memory device decode
always @(MPNMC or CNF or RAM or NextProgAddr or PACntrl or iTBLW
    or ProgReadEnab)
begin
    if ((NextProgAddr[15:9] == 7'b1111111) & CNF)
    begin
        NextPrDpReq = ProgReadEnab;
        NextPwDpReq = PACntrl[13];
    end
    else
    begin
        NextPrDpReq = 0;
        NextPwDpReq = 0;
    end
    if ((NextProgAddr[15:10] >= `C_PR) & (NextProgAddr[15:10] < `C_PR + `C_SR) & RAM)
    begin
        NextPrSpReq = ProgReadEnab;
        NextPwSpReq = PACntrl[13];
    end
    else
    begin
        NextPrSpReq = 0;
        NextPwSpReq = 0;
    end
    if ((NextProgAddr[15:10] < `C_PR) & ~MPNMC)
        NextPrPrReq = ProgReadEnab;
    else
        NextPrPrReq = 0;
    if ((NextProgAddr[15:10] < `C_PR) & (~MPNMC | iTBLW) & PACntrl[13])
        NextPwPrReq = 1;
    else
        NextPwPrReq = 0;
    NextPrExReq = ~(NextPrDpReq | NextPrSpReq | NextPrPrReq) & ProgReadEnab;
    NextPwExReq = ~(NextPwDpReq | NextPwSpReq | NextPwPrReq) & PACntrl[13];
end

// Program data valid
always @(PrProgValid or DpProgValid or SpProgValid or ExProgValid)
    ProgValid = PrProgValid | DpProgValid | SpProgValid | ExProgValid;

// Instruction fetch signal (for NIAQ)
always @(posedge Clock or posedge Reset)
    if (Reset) StartCyc <= 0;
    else StartCyc <= MemCycle | (StartCyc & ~ProgValid);
always @(negedge Clock)
    ProgReadCyc <= StartCyc & ProgValid & ~AddrSourceSel;
always @(Clock or StartCyc or ProgReadCyc)
    InsFetch = ProgReadCyc & StartCyc & ~Clock;

// Program memory read multiplexer
always @(PrDpReq or PrPrReq or PrSpReq or PrExReq or SpRdWrDet
    or B0D or PD or DI or DataWrite)
    if (SpRdWrDet)
        ProgRead = DataWrite;
    else
        ProgRead = ({16{PrDpReq}} & B0D) |
                   ({16{(PrPrReq | PrSpReq)}} & PD) |
                   ({16{PrExReq}} & DI);

// Output bus driver enables
always @(ProgBusEnab or PACntrl or DMAMode or BMARRegCntrl)
begin
    DFCProgEnab = ProgBusEnab & ~(PACntrl[10] & PACntrl[15]);
    StackDataEnab = PACntrl[16];
    StackWriteEnab = PACntrl[17] & ~DMAMode;
    BMARReadEnab = BMARRegCntrl[1];
    BMARProgEnab = PACntrl[10] & PACntrl[15];
end

endmodule