m3s021ct.v

这是16位定点dsp源代码。已仿真和综合过了

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
// Peripheral Memory-Mapped Registers
// Copyright Mentor Graphics Corporation and Licensors 1998.
// V1.002

// Revision history
// V1.002 - 27 June 1997
//          PMMRRdData mux added.

// m3s021ct
// M320C50 Peripheral memory-mapped register decode block.
// Decodes all peripheral memory mapped registers.
//
// Control outputs:
//    SPRegCntrl: 0) DRR write,  1) DXR write,  2) SPC write,
//                3) DRR read,  4) DXR read,  5) SPC read.
//   TimRegCntrl: 0) TIM write,  1) PRD write,  2) TCR write,
//                3) TIM read,  4) PRD read,  5) TCR read.
//  WaitRegCntrl: 0) PDWSR write,  1) IOWSR write,  2) CWSR write,
//                3) PDWSR read,  4) IOWSR read,  5) CWSR read.
//   TDMRegCntrl: 0) TRCV write,  1) TDXR write,  2) TSPC write,
//                3) TCSR write,  4) TRTA write,  5) TRAD write,
//                6) TRCV read,  7) TDXR read,  8) TSPC read.
//                9) TCSR read,  10) TRTA read,  11) TRAD wread.
//

module m3s021ct (WriteAddr, ReadAddr, PMMRWr, PMMRRd,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1998.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//These deliverables may be used for the purpose of making silicon for one  //
//IC design only.  No further use of these deliverables for the purpose of  //
//making silicon from an IC design is permitted without the payment of an   //
//additional license fee.  See your license agreement with Mentor Graphics  //
//for further details.  If you have further questions please contact        //
//Mentor Graphics Customer Support.                                         //
//                                                                          //
//This Mentor Graphics core (m320c50eng v1999.010) was extracted on         //
//workstation hostid 800059c1 Inventra                                      //
    WSGData, TimData, SPData, TSPData,
    SPRegCntrl, TimRegCntrl, WaitRegCntrl, TDMRegCntrl, PMMRRdData);
    input  [6:0] WriteAddr, ReadAddr;
    input        PMMRWr, PMMRRd;
    input [15:0] WSGData, TimData, SPData, TSPData;
    output  [5:0] SPRegCntrl;
    output  [5:0] TimRegCntrl;
    output  [5:0] WaitRegCntrl;
    output [11:0] TDMRegCntrl;
    output [15:0] PMMRRdData;

    reg  [5:0] SPRegCntrl;
    reg  [5:0] TimRegCntrl;
    reg  [5:0] WaitRegCntrl;
    reg [11:0] TDMRegCntrl;
    reg [15:0] PMMRRdData;


// Read/write control decode task
task Decode;
    input [6:0] Addr;
    input [6:0] WriteAddr;
    input [6:0] ReadAddr;
    input       PMMRWr;
    input       PMMRRd;
    output      WriteCntrl;
    output      ReadCntrl;
begin
    if ((WriteAddr == Addr) & PMMRWr) WriteCntrl = 1;
    else WriteCntrl = 0;
    if ((ReadAddr == Addr) & PMMRRd) ReadCntrl = 1;
    else ReadCntrl = 0;
end
endtask


// Address decode
always @(WriteAddr or ReadAddr or PMMRWr or PMMRRd
// Compass synthesizer requires task outputs to be declared in the sensitivity list
or SPRegCntrl or TimRegCntrl or WaitRegCntrl or TDMRegCntrl)
begin
    Decode (7'h20, WriteAddr, ReadAddr, PMMRWr, PMMRRd, SPRegCntrl[0], SPRegCntrl[3]);
    Decode (7'h21, WriteAddr, ReadAddr, PMMRWr, PMMRRd, SPRegCntrl[1], SPRegCntrl[4]);
    Decode (7'h22, WriteAddr, ReadAddr, PMMRWr, PMMRRd, SPRegCntrl[2], SPRegCntrl[5]);
    Decode (7'h24, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TimRegCntrl[0], TimRegCntrl[3]);
    Decode (7'h25, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TimRegCntrl[1], TimRegCntrl[4]);
    Decode (7'h26, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TimRegCntrl[2], TimRegCntrl[5]);
    Decode (7'h28, WriteAddr, ReadAddr, PMMRWr, PMMRRd, WaitRegCntrl[0], WaitRegCntrl[3]);
    Decode (7'h29, WriteAddr, ReadAddr, PMMRWr, PMMRRd, WaitRegCntrl[1], WaitRegCntrl[4]);
    Decode (7'h2A, WriteAddr, ReadAddr, PMMRWr, PMMRRd, WaitRegCntrl[2], WaitRegCntrl[5]);
    Decode (7'h30, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TDMRegCntrl[0], TDMRegCntrl[6]);
    Decode (7'h31, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TDMRegCntrl[1], TDMRegCntrl[7]);
    Decode (7'h32, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TDMRegCntrl[2], TDMRegCntrl[8]);
    Decode (7'h33, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TDMRegCntrl[3], TDMRegCntrl[9]);
    Decode (7'h34, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TDMRegCntrl[4], TDMRegCntrl[10]);
    Decode (7'h35, WriteAddr, ReadAddr, PMMRWr, PMMRRd, TDMRegCntrl[5], TDMRegCntrl[11]);
end

// PMMRRdData output multiplexer
always @(WSGData or TimData or SPData or TSPData)
    PMMRRdData = WSGData | TimData | SPData | TSPData;

endmodule