📄 lcd122x32.lst
字号:
(0038) mov reg[0ah], 00h ; Port_2_GlobalSelect register (PRT2GS)
0387: 62 0A 00 MOV REG[10],0
(0039) M8C_SetBank1
038A: 71 10 OR F,16
(0040) mov reg[0ah], 00h ; Port_2_IntCtrl_0 register (PRT2IC0)
038C: 62 0A 00 MOV REG[10],0
(0041) mov reg[0bh], 00h ; Port_2_IntCtrl_1 register (PRT2IC1)
038F: 62 0B 00 MOV REG[11],0
(0042) M8C_SetBank0
0392: 70 EF AND F,239
(0043) mov reg[09h], 00h ; Port_2_IntEn register (PRT2IE)
0394: 62 09 00 MOV REG[9],0
(0044) M8C_SetBank1
0397: 71 10 OR F,16
(0045) mov reg[0ch], 00h ; Port_3_DriveMode_0 register (PRT3DM0)
0399: 62 0C 00 MOV REG[12],0
(0046) mov reg[0dh], 00h ; Port_3_DriveMode_1 register (PRT3DM1)
039C: 62 0D 00 MOV REG[13],0
(0047) M8C_SetBank0
039F: 70 EF AND F,239
(0048) mov reg[0fh], 00h ; Port_3_DriveMode_2 register (PRT3DM2)
03A1: 62 0F 00 MOV REG[15],0
(0049) mov reg[0eh], 00h ; Port_3_GlobalSelect register (PRT3GS)
03A4: 62 0E 00 MOV REG[14],0
(0050) M8C_SetBank1
03A7: 71 10 OR F,16
(0051) mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
03A9: 62 0E 00 MOV REG[14],0
(0052) mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
03AC: 62 0F 00 MOV REG[15],0
(0053) M8C_SetBank0
03AF: 70 EF AND F,239
(0054) mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
03B1: 62 0D 00 MOV REG[13],0
(0055) M8C_SetBank1
03B4: 71 10 OR F,16
(0056) mov reg[10h], 00h ; Port_4_DriveMode_0 register (PRT4DM0)
03B6: 62 10 00 MOV REG[16],0
(0057) mov reg[11h], 00h ; Port_4_DriveMode_1 register (PRT4DM1)
03B9: 62 11 00 MOV REG[17],0
(0058) M8C_SetBank0
03BC: 70 EF AND F,239
(0059) mov reg[13h], 00h ; Port_4_DriveMode_2 register (PRT4DM2)
03BE: 62 13 00 MOV REG[19],0
(0060) mov reg[12h], 00h ; Port_4_GlobalSelect register (PRT4GS)
03C1: 62 12 00 MOV REG[18],0
(0061) M8C_SetBank1
03C4: 71 10 OR F,16
(0062) mov reg[12h], 00h ; Port_4_IntCtrl_0 register (PRT4IC0)
03C6: 62 12 00 MOV REG[18],0
(0063) mov reg[13h], 00h ; Port_4_IntCtrl_1 register (PRT4IC1)
03C9: 62 13 00 MOV REG[19],0
(0064) M8C_SetBank0
03CC: 70 EF AND F,239
(0065) mov reg[11h], 00h ; Port_4_IntEn register (PRT4IE)
03CE: 62 11 00 MOV REG[17],0
(0066) M8C_SetBank1
03D1: 71 10 OR F,16
(0067) mov reg[14h], 00h ; Port_5_DriveMode_0 register (PRT5DM0)
03D3: 62 14 00 MOV REG[20],0
(0068) mov reg[15h], 00h ; Port_5_DriveMode_1 register (PRT5DM1)
03D6: 62 15 00 MOV REG[21],0
(0069) M8C_SetBank0
03D9: 70 EF AND F,239
(0070) mov reg[17h], 00h ; Port_5_DriveMode_2 register (PRT5DM2)
03DB: 62 17 00 MOV REG[23],0
(0071) mov reg[16h], 00h ; Port_5_GlobalSelect register (PRT5GS)
03DE: 62 16 00 MOV REG[22],0
(0072) M8C_SetBank1
03E1: 71 10 OR F,16
(0073) mov reg[16h], 00h ; Port_5_IntCtrl_0 register (PRT5IC0)
03E3: 62 16 00 MOV REG[22],0
(0074) mov reg[17h], 00h ; Port_5_IntCtrl_1 register (PRT5IC1)
03E6: 62 17 00 MOV REG[23],0
(0075) M8C_SetBank0
03E9: 70 EF AND F,239
(0076) mov reg[15h], 00h ; Port_5_IntEn register (PRT5IE)
03EB: 62 15 00 MOV REG[21],0
(0077) ret
03EE: 7F RET
03EF: 60 28 MOV REG[40],A
03F1: 66 00 ASL [X+0]
03F3: 63 05 65 MOV REG[X+5],101
03F6: 00 SWI
03F7: E6 00 JACC 0x09F8
03F9: E7 00 JACC 0x0AFA
03FB: D6 00 JNC 0x09FC
03FD: B0 00 JNZ 0x03FE
03FF: B1 00 JNZ 0x0500
0401: B2 00 JNZ 0x0602
0403: B3 33 JNZ 0x0737
0405: B4 33 JNZ 0x0839
0407: B5 80 JNZ 0x0988
0409: B6 20 JNZ 0x0A2A
040B: B8 55 JNZ 0xFC61
040D: B9 00 JNZ 0xFD0E
040F: BA 10 JNZ 0xFE20
0411: BB 33 JNZ 0xFF45
0413: BC 33 JNZ 0x0047
0415: BD 00 JNZ 0x0116
0417: BE 00 JNZ 0x0218
0419: 23 00 AND A,[X+0]
041B: 21 10 AND A,16
041D: 22 08 AND A,[i+1]
041F: 27 00 25 AND [X+0],37
0422: 64 ASL A
0423: 26 14 FF AND [_ramareas_end+3],255
0426: 61 00 MOV REG[X+0],A
0428: 69 00 ASR [X+0]
042A: 60 00 MOV REG[0],A
042C: 62 00 67 MOV REG[0],103
042F: 33 68 XOR A,[X+104]
0431: 33 63 XOR A,[X+99]
0433: 00 SWI
0434: 66 00 ASL [X+0]
0436: D1 00 JNC __text_start
0438: D3 00 JNC 0x0739
043A: D0 00 JNC 0x043B
043C: D2 00 JNC 0x063D
043E: E1 1C JACC 0x055B
0440: E2 00 JACC 0x0641
0442: DF 00 JNC 0x0343
0444: DE 00 JNC 0x0245
0446: DD 00 JNC 0x0147
0448: 20 POP X
0449: 21 21 AND A,33
044B: 17 22 05 SUB [X+34],5
044E: 24 21 AND [33],A
0450: 25 16 AND [X+22],A
0452: 26 07 FF AND [i],255
FILE: lib\psocconfig.asm
(0001) ; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
(0002) ;
(0003) ;==========================================================================
(0004) ; PSoCConfig.asm
(0005) ; @PSOC_VERSION
(0006) ;
(0007) ; Version: 0.85
(0008) ; Revised: June 22, 2004
(0009) ; Copyright Cypress MicroSystems 2000-2004. All Rights Reserved.
(0010) ;
(0011) ; This file is generated by the Device Editor on Application Generation.
(0012) ; It contains code which loads the configuration data table generated in
(0013) ; the file PSoCConfigTBL.asm
(0014) ;
(0015) ; DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
(0016) ; Edits to this file will not be preserved.
(0017) ;==========================================================================
(0018) ;
(0019) include "m8c.inc"
(0020) include "memory.inc"
(0021) include "GlobalParams.inc"
(0022)
(0023) export LoadConfigInit
(0024) export _LoadConfigInit
(0025) export LoadConfig_lcd122x32
(0026) export _LoadConfig_lcd122x32
(0027)
(0028) export NO_SHADOW
(0029) export _NO_SHADOW
(0030)
(0031) FLAG_CFG_MASK: equ 10h ;M8C flag register REG address bit mask
(0032) END_CONFIG_TABLE: equ ffh ;end of config table indicator
(0033)
(0034) AREA psoc_config(rom, rel)
(0035)
(0036) ;---------------------------------------------------------------------------
(0037) ; LoadConfigInit - Establish the start-up configuration (except for a few
(0038) ; parameters handled by boot code, like CPU speed). This
(0039) ; function can be called from user code, but typically it
(0040) ; is only called from boot.
(0041) ;
(0042) ; INPUTS: None.
(0043) ; RETURNS: Nothing.
(0044) ; SIDE EFFECTS: Registers are volatile: the A and X registers can be modified!
(0045) ; In the large memory model currently only the page
(0046) ; pointer registers listed below are modified. This does
(0047) ; not guarantee that in future implementations of this
(0048) ; function other page pointer registers will not be
(0049) ; modified.
(0050) ;
(0051) ; Page Pointer Registers Modified:
(0052) ; CUR_PP
(0053) ;
(0054) _LoadConfigInit:
(0055) LoadConfigInit:
(0056) RAM_PROLOGUE RAM_USE_CLASS_4
(0057)
(0058) lcall LoadConfigTBL_lcd122x32_Ordered
0455: 7C 03 40 LCALL 0x0340
(0059) lcall LoadConfig_lcd122x32
0458: 7C 04 5C LCALL 0x045C
(0060)
(0061) RAM_EPILOGUE RAM_USE_CLASS_4
(0062) ret
045B: 7F RET
(0063)
(0064) ;---------------------------------------------------------------------------
(0065) ; Load Configuration lcd122x32
(0066) ;
(0067) ; Load configuration registers for lcd122x32.
(0068) ; IO Bank 0 registers a loaded first,then those in IO Bank 1.
(0069) ;
(0070) ; INPUTS: None.
(0071) ; RETURNS: Nothing.
(0072) ; SIDE EFFECTS: Registers are volatile: the CPU A and X registers may be
(0073) ; modified as may the Page Pointer registers!
(0074) ; In the large memory model currently only the page
(0075) ; pointer registers listed below are modified. This does
(0076) ; not guarantee that in future implementations of this
(0077) ; function other page pointer registers will not be
(0078) ; modified.
(0079) ;
(0080) ; Page Pointer Registers Modified:
(0081) ; CUR_PP
(0082) ;
(0083) _LoadConfig_lcd122x32:
(0084) LoadConfig_lcd122x32:
(0085) RAM_PROLOGUE RAM_USE_CLASS_4
(0086)
(0087) push x
045C: 10 PUSH X
(0088) M8C_SetBank0 ; Force bank 0
045D: 70 EF AND F,239
(0089) mov a, 0 ; Specify bank 0
045F: 50 00 MOV A,0
(0090) asr a ; Store in carry flag
0461: 67 ASR A
(0091) ; Load bank 0 table:
(0092) mov A, >LoadConfigTBL_lcd122x32_Bank0
0462: 50 03 MOV A,3
(0093) mov X, <LoadConfigTBL_lcd122x32_Bank0
0464: 57 EF MOV X,239
(0094) lcall LoadConfig ; Load the bank 0 values
0466: 7C 04 75 LCALL 0x0475
(0095)
(0096) mov a, 1 ; Specify bank 1
0469: 50 01 MOV A,1
(0097) asr a ; Store in carry flag
046B: 67 ASR A
(0098) ; Load bank 1 table:
(0099) mov A, >LoadConfigTBL_lcd122x32_Bank1
046C: 50 04 MOV A,4
(0100) mov X, <LoadConfigTBL_lcd122x32_Bank1
046E: 57 26 MOV X,38
(0101) lcall LoadConfig ; Load the bank 1 values
0470: 7C 04 75 LCALL 0x0475
(0102)
(0103) pop x
0473: 20 POP X
(0104)
(0105) RAM_EPILOGUE RAM_USE_CLASS_4
(0106) ret
0474: 7F RET
(0107)
(0108)
(0109)
(0110)
(0111) ;---------------------------------------------------------------------------
(0112) ; LoadConfig - Set IO registers as specified in ROM table of (address,value)
(0113) ; pairs. Terminate on address=0xFF.
(0114) ;
(0115) ; INPUTS: [A,X] points to the table to be loaded
(0116) ; Flag Register Carry bit encodes the Register Bank
(0117) ; (Carry=0 => Bank 0; Carry=1 => Bank 1)
(0118) ;
(0119) ; RETURNS: nothing.
(0120) ;
(0121) ; STACK FRAME: X-4 I/O Bank 0/1 indicator
(0122) ; X-3 Temporary store for register address
(0123) ; X-2 LSB of config table address
(0124) ; X-1 MSB of config table address
(0125) ;
(0126) LoadConfig:
(0127) RAM_PROLOGUE RAM_USE_CLASS_2
(0128) add SP, 2 ; Set up local vars
0475: 38 02 ADD SP,2
(0129) push X ; Save config table address on stack
0477: 10 PUSH X
(0130) push A
0478: 08 PUSH A
(0131) mov X, SP
0479: 4F MOV X,SP
(0132) mov [X-4], 0 ; Set default Destination to Bank 0
047A: 56 FC 00 MOV [X-4],0
(0133) jnc .BankSelectSaved ; Carry says Bank 0 is OK
047D: D0 04 JNC 0x0482
(0134) mov [X-4], 1 ; No Carry: default to Bank 1
047F: 56 FC 01 MOV [X-4],1
(0135) .BankSelectSaved:
(0136) pop A
0482: 18 POP A
(0137) pop X
0483: 20 POP X
(0138)
(0139) LoadConfigLp:
(0140) M8C_SetBank0 ; Switch to bank 0
0484: 70 EF AND F,239
(0141) M8C_ClearWDT ; Clear the watchdog for long inits
0486: 62 E3 00 MOV REG[227],0
(0142) push X ; Preserve the config table address
0489: 10 PUSH X
(0143) push A
048A: 08 PUSH A
(0144) romx ; Load register address from table
048B: 28 ROMX
(0145) cmp A, END_CONFIG_TABLE ; End of table?
048C: 39 FF CMP A,255
(0146) jz EndLoadConfig ; Yes, go wrap it up
048E: A0 1F JZ 0x04AE
(0147) mov X, SP ;
0490: 4F MOV X,SP
(0148) tst [X-4], 1 ; Loading IO Bank 1?
0491: 48 FC 01 TST [X-4],1
(0149) jz .IOBankNowSet ; No, Bank 0 is fine
0494: A0 03 JZ 0x0498
(0150) M8C_SetBank1 ; Yes, switch to Bank 1
0496: 71 10 OR F,16
(0151) .IOBankNowSet:
(0152) mov [X-3], A ; Stash the register address
0498: 54 FD MOV [X-3],A
(0153) pop A ; Retrieve the table address
049A: 18 POP A
(0154) pop X
049B: 20 POP X
(0155) inc X ; Advance to the data byte
049C: 75 INC X
(0156) adc A, 0
049D: 09 00 ADC A,0
(0157) push X ; Save the config table address again
049F: 10 PUSH X
(0158) push A
04A0: 08 PUSH A
(0159) romx ; load config data from the table
04A1: 28 ROMX
(0160) mov X, SP ; retrieve the register address
04A2: 4F MOV X,SP
(0161) mov X, [X-3]
04A3: 59 FD MOV X,[X-3]
(0162) mov reg[X], A ; Configure the register
04A5: 61 00 MOV REG[X+0],A
(0163) pop A ; retrieve the table address
04A7: 18 POP A
(0164) pop X
04A8: 20 POP X
(0165) inc X ; advance to next table entry
04A9: 75 INC X
(0166) adc A, 0
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