📄 boot.lis
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0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 and reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
00F8 bSSC_KEY1: equ F8h ; supervisory key
00F9 bSSC_KEYSP: equ F9h ; supervisory stack ptr key
00FA bSSC_TABLE_TableId: equ FAh ; table ID
0000
003A OPER_KEY: equ 3Ah ; operation key
0000
0000 ;----------------------------------
0000 ; SSC_Action macro command codes
0000 ;----------------------------------
0001 FLASH_READ: equ 1 ; flash read command
0002 FLASH_WRITE: equ 2 ; flash write command
0003 FLASH_ERASE: equ 3 ; flash erase command
0004 PROTECT_BLOCK: equ 4 ; flash protect block command
0006 TABLE_READ: equ 6 ; table read command
0007 FLASH_CHECKSUM: equ 7 ; flash checksum calculation command
0008 CALIBRATE0: equ 8 ; Calibrate without checksum
0009 CALIBRATE1: equ 9 ; Calibrate with checksum
0000
0000 ;----------------------------------
0000 ; SSC_Action Flash table addresses
0000 ;----------------------------------
0000 ; Table 0 Values
00F8 SILICON_ID_1: equ F8h ; Table 0 first byte of silicon ID
00F9 SILICON_ID_0: equ F9h ; Table 0 second byte of silicon ID
0000
0000 ; Table 1 Values
00F8 SSCTBL1_TRIM_BGR_3V: equ F8h ; 3.3V bandgap ref voltage trim
00F9 SSCTBL1_TRIM_IMO_3V_24MHZ: equ F9h ; 3.3V internal main oscillator trim (24MHz)
00FA SSCTBL1_CAL_ROOM_3V: equ FAh ; 3.3V Room Temp Calibration
00FB SSCTBL1_CAL_HOT_3V: equ FBh ; 3.3V Hot Temp Calibration
00FC SSCTBL1_TRIM_BGR_5V: equ FCh ; 5.0V bandgap ref voltage trim
00FD SSCTBL1_TRIM_IMO_5V_24MHZ: equ FDh ; 5.0V internal main oscillator trim (24MHz)
00FE SSCTBL1_CAL_ROOM_5V: equ FEh ; 5.0V Room Temp Calibration
00FF SSCTBL1_CAL_HOT_5V: equ FFh ; 5.0V Hot Temp Calibration
0000 ; legacy names:
00F8 VOLTAGE_TRIM_3V: equ F8h ; Table 1 3.3V bandgap ref voltage trim value
00F9 OSCILLATOR_TRIM_3V: equ F9h ; Table 1 3.3V internal main oscillator trim value
00FC VOLTAGE_TRIM_5V: equ FCh ; Table 1 5.0V bandgap ref voltage trim value
00FD OSCILLATOR_TRIM_5V: equ FDh ; Table 1 5.0V internal main oscillator trim value
0000
0000 ; Table 2 Values
00F8 SSCTBL2_TRIM_BGR_2V: equ F8h ; 2.7V bandgap ref voltage trim
00F9 SSCTBL2_TRIM_IMO_2V_12MHZ: equ F9h ; 2.7V internal main oscillator trim (12MHz)
00FA SSCTBL2_CAL_ROOM_2V: equ FAh ; 2.7V Room Temp Calibration
00FB SSCTBL2_CAL_HOT_2V: equ FBh ; 2.7V Hot Temp Calibration
00FC SSCTBL2_TRIM_IMO_3V_6MHZ: equ FCh ; 3.3V IMO Trim for SLOWIMO 6MHz operation
00FD SSCTBL2_TRIM_IMO_2V_6MHz: equ FDh ; 2.7V IMO Trim for SLOWIMO 6MHz operation
00FE SSCTBL2_TRIM_IMO_5V_6MHZ: equ FEh ; 5.0V IMO Trim for SLOWIMO 6MHz operation
0000 ; legacy names:
00F8 VOLTAGE_TRIM_2V: equ F8h ; Table 2 2.7V bandgap voltage trim value
00F9 OSCILLATOR_TRIM_SLOW_2V_12MHZ: equ F9h ; Table 2 2.7V SLOW IMO Trim 12MHz, 2.7V
00FC OSCILLATOR_TRIM_SLOW_3V_6MHZ: equ FCh ; Table 2 2.7V SLOW IMO Trim 6MHz, 3.3V
00FD OSCILLATOR_TRIM_SLOW_2V_6MHZ: equ FDh ; Table 2 2.7V SLOW IMO Trim 6MHz, 2.7V
0000
0000
0000 ;-----------------------------------------------------------------------------
0000 ; MACRO SSC_Action( OpCode )
0000 ;
0000 ; DESCRIPTION:
0000 ; Performs supervisory operations defined in Supervisory ROM (SROM)
0000 ; section of Technical Reference Manual and/or Datasheet.
0000 ;-----------------------------------------------------------------------------
0000 ;
0000 ; ARGUMENTS:
0000 ; BYTE OpCode - specified supervisory operation - defined operations
0000 ; are: FLASH_WRITE, FLASH_ERASE, FLASH_READ, TABLE_READ,
0000 ; FLASH_CHECKSUM, PROTECT_BLOCK
0000 ; RETURNS:
0000 ; Nothing
0000 ;
0000 ; SIDE EFFECTS:
0000 ; The values of the A and X registers are modified
0000 ;
0000 ; PROCEDURE:
0000 ; 1) specify a 3 byte stack frame. Save in [KEYSP]
0000 ; 2) insert the flash Supervisory key in [KEY1]
0000 ; 3) store function code in A
0000 ; 4) call the supervisory code
0000 ;
0000 macro SSC_Action( OpCode )
0000 ; !!! DO NOT CHANGE THIS CODE !!!
0000 ; This sequence of opcodes provides a
0000 ; signature for the debugger and ICE.
0000 mov X, SP ; copy SP into X
0000 mov A, X ; mov to A
0000 add A, 3 ; create 3 byte stack frame
0000 mov [bSSC_KEYSP], A ; save stack frame for supervisory code
0000 mov [bSSC_KEY1], OPER_KEY ; load the code for supervisory operations
0000 mov A, @OpCode ; load A with specific Flash operation
0000 SSC ; SSC call the supervisory code
0000 ; !!! DO NOT CHANGE THIS CODE !!!
0000 macro M8SSC_SetTableTrims( Table, IMO_Trim, Volt_Trim, Bypass )
0000 mov [bSSC_TABLE_TableId], @Table ; Point to requested Flash Table
0000 SSC_Action TABLE_READ ; Perform a table read supervisor call
0000 M8C_SetBank1
0000 mov A, [@IMO_Trim]
0000 mov reg[IMO_TR], A ; Load the 3V trim oscillator setting
0000 mov A, [@Volt_Trim]
0000 IF ( @Bypass )
0000 or A, AGND_BYPASS_MASK ; OR in the bypass setting
0000 ENDIF
0000 mov reg[BDG_TR], A ; Load the bandgap trim setting for 3V
0000 M8C_SetBank0
0000 macro M8SSC_Set2TableTrims( TableA, IMO_Trim, TableB, Volt_Trim, Bypass )
0000 mov [bSSC_TABLE_TableId], @TableA ; Point to Flash Table for IMO Trim
0000 SSC_Action TABLE_READ ; Copy table data to RAM F8-FF
0000 M8C_SetBank1 ; (Note, preserved across next SSC!)
0000 mov A, [@IMO_Trim] ; Set the main oscillator trim
0000 mov reg[IMO_TR], A
0000 mov [bSSC_TABLE_TableId], @TableB ; Point to Flash Table for Volt Trim
0000 SSC_Action TABLE_READ ; Copy table data to RAM F8-FF
0000 mov A, [@Volt_Trim] ; Set the bandgap voltage trim
0000 IF ( @Bypass )
0000 or A, AGND_BYPASS_MASK ; OR in the bypass setting
0000 ENDIF
0000 mov reg[BDG_TR], A ; Load the bandgap trim setting for 3V
0000 M8C_SetBank0
0000 macro M8SSC_SetTableVoltageTrim( Table, Volt_Trim, Bypass )
0000 mov [bSSC_TABLE_TableId], @Table ; Point to Flash Table
0000 SSC_Action TABLE_READ ; Perform a table read supervisor call
0000 M8C_SetBank1
0000 mov A, [@Volt_Trim] ; Get the bandgap trim seting
0000 IF ( @Bypass )
0000 or A, AGND_BYPASS_MASK ; OR in the bypass setting, if any
0000 ENDIF
0000 mov reg[BDG_TR], A ; Update the register value
0000 M8C_SetBank0
0000 macro M8SSC_SetTableIMOTrim( Table, IMO_Trim )
0000 mov [bSSC_TABLE_TableId], @Table ; Point to Flash Table 1
0000 SSC_Action TABLE_READ ; Perform a table read supervisor call
0000 M8C_SetBank1
0000 mov A, [@IMO_Trim] ; Get the IMO trim seting
0000 mov reg[IMO_TR], A ; Update the register value
0000 M8C_SetBank0
0000 SYSTEM_STACK_PAGE: equ 0
0000 SYSTEM_STACK_BASE_ADDR: equ 0h
0000 SYSTEM_LARGE_MEMORY_MODEL: equ 0
0001 SYSTEM_SMALL_MEMORY_MODEL: equ 1
0001 SYSTEM_TOOLS: equ 1
0001 SYSTEM_IDXPG_TRACKS_STK_PP: equ 1
0000 SYSTEM_IDXPG_TRACKS_IDX_PP: equ 0
0000 ⌨️ 快捷键说明
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