i2cm_io.asm

TI 281x DSP 各种通信接口驱动源代码

;=====================================================================
;
; File Name     : I2CM_IO.ASM
; 
; Originator    : Digital Control Systems Group 
;                 Texas Instruments 
; 
; Description   : This file contains Virtual I2C Master implementation
;                 in software. 
;
; Routine Type  : "CcA Only"
;                               
; Target        : C28x
;
; Date          : 30/01/2002 (DD/MM/YYYY)
;=====================================================================
;typedef struct {   
;       unsigned int taskIndex;  /* Index into the task pointers    */
;       unsigned int I2CCSR;     /* I2C Control & Status register (LSB-bit counter) */
;       unsigned int I2CDAT;     /* I2C Shift Register              */
;       unsigned int bitCntr;    /* Bit Counter                     */  
;       void (*init)(void *);    /* Initialisation routine          */
;       void (*tick)(void *);    /* I2C tick function               */
;       }VI2CM_IO;  
;=====================================================================
        .include "..\include\i2cmpin.h"       
;=====================================================================
; Module definition for external referance
            .def    _vi2cmInit
            .def    _vi2cmTick
;=====================================================================

;=====================================================================
; i2cmTick : Initialization function
;======================================================================
_vi2cmInit:
		EALLOW
        MOVL    XAR6,#SCL_DIR           ; XAR5->GPIO direction register for SCL
        MOVL    XAR5,#SDA_DIR           ; XAR4->GPIO direction register for SDA

        TCLR    *+XAR6[0],#(SCL_BIT)  ; Set the SCL pin as input
        TCLR    *+XAR5[0],#(SDA_BIT)  ; Set the SDA pin as input
        
        MOVL    XAR6,#SCL_MUX           ; XAR5->GPIO MUX control register for SCL
        MOVL    XAR5,#SDA_MUX           ; XAR4->GPIO MUX control register for SDA
        

        TCLR    *XAR5,#(SDA_BIT)      ; Configure SDA pin in GPIO mode
        TCLR    *XAR6,#(SCL_BIT)        ; Configure SCL pin in GPIO mode        
		
        MOV     *XAR4++,#IDLE_INDEX 
        MOV     *XAR4++,#0              ; I2CCSR=0
        MOV     *XAR4++,#0              ; I2CDAT=0
        MOV     *XAR4++,#0              ; bitCntr=0
		EDIS
        LRETR

;======================================================================
; i2cmTick : Periodic tick function
;======================================================================
;======================================================================
; Entry Condition
; AR4=Module Handle
;======================================================================
_vi2cmTick:
		EALLOW
        MOVZ    AR0,*+XAR4[0]           ; AR0=taskIndex
        MOVL    XAR5,#TASK_PTR
        MOVL    XAR7,*+XAR5[AR0]        ; XAR7=task[taskIndex]
        MOVL    XAR6,#SCL_DIR           ; XAR5->GPIO direction register for SCL
        MOVL    XAR5,#SDA_DIR           ; XAR4->GPIO direction register for SDA
        MOVB    AR0,#31,UNC            ; AR0->offset for data register
        LB      *XAR7

;=========================================================================
; Issue Start Condition
; STATE 1: Check for SDA and SCL HIGH
;=========================================================================
START_S1:           
        MOV     *+XAR4[0],#START_S3_INDEX   
        TBIT    *+XAR6[AR0],#SCL_BIT
        MOVB    *+XAR4[0],#START_S2_INDEX,NTC       
        TBIT    *+XAR5[AR0],#SDA_BIT
        MOVB    *+XAR4[0],#START_S2_INDEX,NTC 
        EDIS   
        LRETR

;=========================================================================
; Issue Start Condition
; STATE 2: De-Assert SDA & SCL lines 
;=========================================================================
START_S2:
        TCLR    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as input
        TCLR    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as input
        MOV     *+XAR4[0],#START_S1_INDEX   ; Update the Task to next state  
        EDIS   
        LRETR

;=========================================================================
; Issue Start Condition
; STATE 3: Drive SDA pin LOW
;=========================================================================
START_S3:   
        TSET    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as output
        TCLR    *+XAR5[AR0],#SDA_BIT        ; Drive the SDA pin LOW             
        MOV     *+XAR4[0],#START_S4_INDEX   ; Update the Task to next state  
        EDIS   
        LRETR

;=========================================================================
; Issue Start Condition
; STATE 4: Drive SCL pin LOW 
;=========================================================================

START_S4:
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL  pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 
        MOV     *+XAR4[0],#IDLE_INDEX       ; Update the Task to next state  
        EDIS   
        LRETR

;=========================================================================
; Issue Stop Condition
; STATE 1: Drive SDA pin LOW
;=========================================================================
STOP_S1:       
        TSET    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as output
        TCLR    *+XAR5[AR0],#SDA_BIT        ; Drive the SDA pin LOW          
        MOV     *+XAR4[0],#STOP_S2_INDEX    ; Update the Task to next state  
        EDIS   
        LRETR

;=========================================================================
; Issue Stop Condition
; STATE 2: De-assert SCL pin, move to next state if SCL is sampled HIGH
;=========================================================================
STOP_S2:
        TCLR    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as input
        TBIT    *+XAR6[AR0],#SCL_BIT    
        MOVB    *+XAR4[0],#STOP_S3_INDEX,TC      
        EDIS   
        LRETR
        
;=========================================================================
; Issue Stop Condition
; STATE 3: De-assert SDA pin, move to next state if SDA is sampled HIGH
;=========================================================================
STOP_S3: 
        TCLR    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as input
        TBIT    *+XAR5[AR0],#SDA_BIT    
        MOVB    *+XAR4[0],#IDLE_INDEX,TC         
        EDIS   
        LRETR

;=========================================================================
; Issue Sr condition (Repeated Start)
; STATE 1: Drive SCL pin LOW
;=========================================================================
RSTART_S1:
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 
        MOV     *+XAR4[0],#RSTART_S2_INDEX  ; Update the Task to next state  
        EDIS   
        LRETR

;=========================================================================
; Issue Sr condition (Repeated Start)
; STATE 2: De-assert SDA pin, move to next state if it is sampled HIGH
;=========================================================================
RSTART_S2:
        TCLR    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as input
        TBIT    *+XAR5[AR0],#SDA_BIT    
        MOVB    *+XAR4[0],#RSTART_S3_INDEX,TC        
        EDIS   
        LRETR

;=========================================================================
; Issue Sr condition (Repeated Start)
; STATE 3: De-assert SCL pin, move to STATE2 if it is sampled HIGH
;=========================================================================
RSTART_S3:
        TCLR    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as input
        TBIT    *+XAR6[AR0],#SCL_BIT    
        MOVB    *+XAR4[0],#START_S3_INDEX,TC         
        EDIS   
        LRETR

;=========================================================================
; Issue Acknowledge
; STATE 1: Drive SCL LOW and then Drive SDA pin using ACKDT
;=========================================================================
ACK_S1:
        TSET    *+XAR6[0],#(SCL_BIT)      ; Set the SCL pin as output
        TCLR    *+XAR6[AR0],#SCL_BIT        ; Drive the SCL pin LOW 
        
        TBIT    *+XAR4[1],#ACKDT_BIT
        SBF     SEND_ACK_HI,TC
        
        MOV    *+XAR4[0],#ACK_S2_INDEX 
        TSET    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as output
        TCLR    *+XAR5[AR0],#SDA_BIT        ; Drive the SDA pin LOW             
        EDIS   
        LRETR

SEND_ACK_HI:
        TCLR    *+XAR5[0],#(SDA_BIT)      ; Set the SDA pin as input
        TBIT    *+XAR5[AR0],#SDA_BIT    
        MOVB    *+XAR4[0],#ACK_S2_INDEX,TC          
        EDIS   
        LRETR

;=========================================================================
; Issue Acknowledge
; STATE 2: De-assert SCL